A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn calls other microinstruction sequences for deriving pointers representing the location of the called procedure and of arguments from operands in the call instruction. As the call microcode obtains each argument pointer, it places the pointer on the stack. After it has obtained all of the argument pointers, it passes the pointer to the called procedure and a pointer to the argument pointers to a general call microinstruction sequence. That microinstruction sequence locates the called procedure, makes a new frame including the argument pointers, and saves the state necessary to resume execution of the call microinstruction sequence itself. It then obtains the state necessary to commence execution of the called procedure and causes execution of that procedure to commence. The microcode corresponding to the return instruction restores both the state necessary to resume execution of the calling procedure and the state necessary to resume execution of the call microinstruction sequence. When it resumes execution, the call microinstruction sequence completes the return operation.

A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

A computer architecture is disclosed which permits intersegment program calls with associated selective allocation of data segments of varying lengths. The calling program controls selective allocation of segments to the called program but the called program controls the lengths of the segments being allocated. In this way, recursive calls to the same program cannot affect the function or data of other programs or of the same program in a previous call. Also allocation of data segments can be postponed until execution resulting in more flexible execution of programs written without knowledge of the details of other co-executing programs.

A debugging microprocessor used in an in-circuit emulator is made to be capable of moving into a debugging interrupt processing execution mode in response to an external supervisor interrupt instruction. This debugging microprocessor comprises a first program counter put in an operating condition when the microprocessor is in a user's program execution mode, a second program counter put in an operating condition when the microprocessor is in a debugging interrupt processing execution mode, and a program counter controller responding to the external supervisor interrupt instruction to cause a content of the second program counter to be outputted as a program counter value. The program counter controller also responds to a return instruction to cause a content of the first program counter to be outputted as a program counter value. Thus, the content of the first program counter can be accessed in the course of the debugging interrupt processing execution.

A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information corresponding to the operating environment for the calling routine and then utilizes corresponding information in the subroutine to establish the operating environment for the subroutine. A common return instruction at the completion of each subroutine causes the central processor to retrieve the saved operating information thereby to reestablish the operating environment for the calling routine.