Zero adjustment of second information in an electronic timepiece is carried out upon receiving a command from the operator. "Increment one" is performed upon minute information when the second information is between 24 and 59 seconds when the zero adjustment command is generated. Minute information is not changed when the second information is between 0 and 23 seconds when the zero adjustment command is generated.
An electronic timepiece has a timepiece standard generator, a frequency divider having a resettable terminal, a circuit for controlling an optically displaying device connected to the frequency divider, a circuit for controlling a hand displaying device connected to the frequency divider, a below second linking control circuit for detecting first the content of the frequency divider in response to the operation of either first switch for resetting to zero the digit of second of the optically displaying device or second switch for initiating to act the hand displaying device and for resetting next to zero the digit of second of the optically displaying device and initiating to act the hand displaying device after the time adjustment of the hand displaying device respectively. At the time of detection of a below second linking control circuit, the below second linking control circuit controls to advance by one second on the hand displaying device if the content of the frequency divider is 0.5 seconds and over at the resetting state of second-digit of the optically displaying device and controls to advance by one second on the optically displaying device if the content of the frequency divider is 0.5 seconds and over at the stepping state of the hand displaying device, whereby after the adjustment of either the optically displaying device or the hand displaying device, the time indication of the optically displaying device is linked to the time indication of the hand displaying device within 0.5 seconds.
A time correction circuit for an electronic timepiece comprising an oscillator circuit inputting a high frequency standard signal to a divider network, the divider network dividing down the standard signal in a plurality of stages. Correction data is periodically applied to a plurality of divider stages to advance or retard the timing rate when a selected stage achieves a preferred logic state. Occurrence of a logic state in a subsequent divider stage enables the circuits for the next periodic application of the correcting data. Coarse and fine adjustments can be made.
