A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address inputs of a dual port descriptor memory which stores descriptors. Two descriptors are simultaneously fetched from locations of the descriptor memory determined by the first and second address fields of the microinstruction. Each descriptor includes an address field which defines a location of the least significant bit of an operand in the scratch pad memory and a length field which defines the length of that operand. Two operands or partial operands are fetched from the scratch pad memory and transferred to a rotator circuit which automatically aligns the fetched operand to an arithmetic and logic unit which performs iterative and fractional operations. The disclosed system and method permit interpretation of virtual instructions without utilizing additional firmware subroutines to accomplish shifting or masking of variable length operands or to perform iterative operations or carry safe operations involving the operands to align them with fixed width hardware of the processor.
A computer system and method for storing data in pages of memory according to a data structure which is stored within the memory and identifies the pages of data. The data structure includes a beginning buffer pointer and an ending buffer pointer. The beginning and ending buffer pointers have page address portions and base address portions. The base address portion of the beginning buffer pointer is changed each time a data location is accessed. The page address portion of the beginning buffer pointer is replaced with the page address portion of the ending buffer pointer when the base address portion of the beginning buffer pointer reaches a page boundary.
A programmable digital controller has an address matrix memory (20) and an instruction matrix memory (10). The address memory stores address words each having the address of the first sample and the number of samples in a unique group of samples. Unique groups of samples are sequentially stored in an instruction matrix memory. Each column of the instruction memory has data bits for regenerating an instruction set for controlling any one of many apparatus or processes. Each row of the instruction memory has a sample from each instruction set. In response to an enabling signal, the words from the address memory are sequentially read, interpreted, and the samples from the instruction memory caused to be read and for reconstructing the instruction set.
The alignment of data as required in an L-stage is carried out with a first aligner which is controlled by a wired logic for exclusive use, while the alignment of data as required in an E-stage is carried out with a second aligner which is controlled by a microinstruction. Regarding those among macroinstructions which need to fetch storage operands in only the L-stages, the alignment of the storage operand is carried out by means of the first aligner. On the other hand, in the execution of macroinstructions which need to fetch storage operands in both the L-stages and the E-stages, the storage operands fetched in the L- and E-stages are respectively aligned by means of the first and second aligners.
In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM unit includes an input buffer unit and an output buffer unit, a control unit to analyze an incoming DATA and provide appropriate control signals, a reconfiguration unit for reformatting the plurality of descriptor formats into a composite format, a descriptor fetch unit for retrieving a descriptor when the signals applied to the VMSM unit contain a descriptor address, and a descriptor master copy unit which contains a copy of the descriptors stored in the addressing apparatus.
A data processing system has an arithmetic operating unit to process a plurality of bytes at a time and carries out an arithmetic operation on first and second operands each starting from any desired address on a main memory and having any desired number of byte length. The second operand is aligned to an operand position of the first operand and the aligned second operand is supplied to the operating unit while the first operand is supplied as it is to the operating unit. Since the second operand is aligned to the operand position of the first operand before it is processed in the operating unit, the number of times of alignment is reduced.
