A microprocessor based apparatus for use as a bus controller and as a remote terminal in a time-division multiplex serial data bus system. The apparatus comprises a single chip which, in a preferred embodiment, is in the form of radiation hardened LSI/CMOS/SOS. It operates on a one bit per instruction basis and includes program control of output signals and word length. The described embodiment is program adapted to satisfy the performance requirements of the applicable military standard, but is easily modified, by changing the contents of an external expandable instruction storage device, to accommodate alternative requirements such as different word lengths, different message formats, and even different bus protocols. A data format encoder and data format decoder provide means to convert from Manchester bi-phase data to NRZ data for receiving data from the data bus and to make the opposite conversion for transmitting data over the data bus.
An improved modem is operative for interfacing a computer subsystem with a data bus system. The computer subsystem may be designed-to process digital information in accordance with certain timing criteria that is incompatible with the operational timing criteria of the data bus system. The modem includes a programmable subsystem interface that permits interfacing the subsystem's timing criteria with the data bus system's timing criteria.
A bus interface unit for use with a multiplexed biphase serial bus includes a Mealy modeled sequence logic unit which allows flexibility in the design and implementation of a desired data transfer algorithm. The unit's internal architecture is such that the device may be implemented on a single semiconductor chip.
An I/O controller for transferring data between a host processor and one or more I/O devices. This I/O controller includes a microprocessor, a direct memory access controller and a dual port storage unit, one port of which is coupled to the host processor I/O channel bus and the other port of which is coupled to the microprocessor bus. All data transfers are by way of the dual port storage unit. The I/O controller includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between the host processor and the I/O controller. In particular, this interleaving mechanism enables host processor direct program control (DPC) data transfers to be performed at the same time that the I/O controller is busy doing cycle steal data transfers for a block of data. These DPC data transfers are accomplished without interrupting the cycle stealing operations.
A radio system (100) includes a plurality of addressable processors (150, 180, and 200). A communication link (230) interconnects the addressable processors (150, 180, and 200). The communication between the addressable processors is conducted via a first and a second communication protocols. The first communication protocol includes a plurality of fixed length information packets for passing parametric data to or from the addressable processors at a fixed baud rate including a packet for changing the communication protocol. The second communication protocol includes a plurality of variable length information packets for passing parametric data to or from the addressable processors at selectable speeds. Whereby the operating state of the addressable processors may be determined or altered by, respectively, communicating parametric data from or to the addressable processor at variable baud rates.
A bus device of a first type uses a first arbitration protocol. The first-type device is designed for use in a computer system having a communications bus, and one or more other bus devices connected to the bus, including possible first-type bus devices which also use the first arbitration protocol and one or more second-type bus devices which use a second, different, arbitration protocol. The first-type bus device includes a protocol specific memory for storing information; means for monitoring the bus to determine whether the current bus master of the bus arbitrated in the manner of the first or second arbitration protocols; and means for denying the current bus master the ability to access information stored in the protocol specific memory if the means for monitoring determines the bus master arbitrated according to the second arbitration protocol.
