Binary input data or analog voltages are processed in parallel paths to form a bi-level (coarse and fine) output. A binary input is parallel processed to produce an analog current output and an analog input is parallel processed to produce a binary coded output. For binary-to-analog conversion, analog multiplexing and scaling adjusts the fine current to the coarse current prior to summing into a composite analog output. An analog input is continuously available to a comparator that senses voltage levels and reference voltages to provide binary coded linear scale pulses for parallel processing into fine increments of a binary output and coarse increments of a binary output combined into a total binary coded output.
A method and apparatus for testing the linearity of a digital-to-analog converter that uses equally-weighted signal sources to convert high-order bits of digital input, and unequally-weighted signal sources to convert low-order bits. Minimum and maximum digital inputs are supplied, and a linear input-output characteristic is calculated from the two resulting analog output values. The nonlinearity error is calculated by finding the deviations from this linear input-output characteristic of two sets of analog output values: one set obtained by varying the high-order bits while holding the low-order bits constant; the other set obtained by varying the low-order bits while holding the high-order bits constant.
A multi-channel D/A converter is formed with a plurality of converter units, each having one single input transistor and a plurality of output transistors which together form current mirrors. Mutually corresponding ones of these output transistors of different ones of the converter units, which are switched on and off together, are disposed adjacently and connected together to a trunk power supply line such that the parasitic resistances through the conductive lines connected to the output transistors are alike and the conversion characteristics of the individual converter units also become alike. One common input transistor may be shared by all of the converter units for further improving the conversion characteristic.
This circuit arrangement includes an interpolation filter (3) which converts the incoming signal values (A) into interpolated signal values (B) of increased repetition frequency. The interpolated signal values (B) are reduced in word length by means of a quantizer (4a) and by quantization error feedback through an error filter (25). A D/A converter (6) consists of two or more nonweighted switching stages connected in parallel. The activated switching stages deliver currents which are added together at the output end. The D/A converter (6) is controlled by a control circuit (5) which processes the output signals (D) of the quantizer (4a). The activated switching stages are continuously interchanged on a cyclic basis, so that relative resistance tolerances in the circuit average out.
In an A/D converter, a resistive network for producing 2.sup.n different voltage steps. The resistive network includes a coarse relatively high impedance resistive string which is subdivided into 2.sup.x coarse segments. The resistive network also includes a fine relatively high impedance resistive network comprised of a fine resistive element per coarse segment. Each fine resistive element is then subdivided into 2.sup.(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only the fine segment in parallel with the "bracketing" coarse resistor is then coupled to comparator means to sense which fine sub-segment brackets the input voltage.
A circuit for calibrating a coarse channel circuit in a folding analog-to-digital converter circuit. A reference value is input to the coarse channel circuit and an output of the coarse channel circuit is sensed. A parameter of the coarse channel circuit is adjusted until the coarse channel circuit is successfully calibrated.
