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Claims  |
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What is claimed is:
1. In a time division multiplex transmission system including a central
unit and a plurality of terminal units, said central unit transmitting at
least address signals and control signals respectively in a set
sequentially to respective ones of said terminal units, each of said
terminal units responding to a corresponding address signal which
accompanies each control signal and receiving said control signal to be
thereby controlled and transmitting to the central unit a response signal
in accordance with the control signal, and said address, control and
response signals being arranged as time-divided in a series time band; an
arrangement in which said terminal units are respectively provided with
means for accumulating therein an electric power required for operating
the terminal unit and supplying said accumulated power to the terminal
unit, said electrical power being transmitted from the central unit
accompanying at least the address and control signals, wherein a direct
current voltage higher than a required voltage for each terminal unit is
transmitted from the central unit as superposed at least on the address
and control signals and at least during the period of transmitting the
signals.
2. In a time division multiplex transmission system including a central
unit and a plurality of terminal units, said central unit transmitting at
least address signals and control signals respectively in a set
sequentially to respective ones of said terminal units, each of said
terminal units responding to a corresponding address signal which
accompanies each control signal and receiving said control signal to be
thereby controlled and transmitting to the central unit a response signal
in accordance with the control signal, and said address, control and
response signals being arranged as time-divided in a series time band; an
arrangement in which said terminal units are respectively provided with
means for accumulating therein an electric power required for operating
the terminal unit and supplying said accumulated power to the terminal
unit, said electric power being transmitted from the central unit
accompanying at least the address and control signals, wherein a
predetermined voltage signal is transmitted from the central unit to a
respective terminal unit also during transmissions of the response signals
from the respective terminal units, the response signal is transmitted in
the form of a current signal by short-circuiting and opening a circuit of
the respective terminal units, and said electric power accumulating means
accumulates the power also during transmissions of the response signals.
3. In a time division multiplex transmission system including a central
unit and a plurality of terminal units, said central unit transmitting at
least address signals and control signals respectively in a set
sequentially to respective ones of said terminal units, each of said
terminal units reponding to a corresponding address signal which
accompanies each control signal and receiving said control signal to be
thereby controlled and transmitting to the central unit a response signal
in accordance with the control signal, and said address, control and
response signals being arranged as time-divided in a series time band; an
arrangement in which said terminal units are respectively provided with
means for accumulating therein an electric power required for operating
the terminal unit and supplying accumulated power to the terminal unit,
said electric power being transmitted from the central unit accompanying
at least the address and control signals, wherein a direct current voltage
higher than a required voltage for each terminal unit is transmitted from
the central unit as superposed at least on the address and control signals
and at least during the period of transmitting the signals, further
wherein a predetermined voltage signal is transmitted from the central
unit to the terminal unit also during the transmission of the response
signal from the respective terminal units, the response signal is
transmitted in the form of a current signal by short-circuiting and
opening a circuit of the respective terminal units, and said electric
power accumulating means accumulates the power also during transmissions
of the response signals.
4. In a time division multiplex transmission system including a central
unit and a plurality of terminal units, said central unit transmitting at
least address signals and control signals respectively in a set
sequentially to respective ones of said terminal units, each of said
terminal units which corresponds to each address signal which accompanies
each control signal receiving said control signal to be thereby controlled
and transmitting to the central unit a response signal in accordance with
the control signal, and said address, control and response signals being
arranged as time-divided in a series time band; an arrangement in which
said terminal units are respectively provided with means for accumulating
therein an electric power required for operating the terminal unit and
supplying said power accumulated to the terminal unit, said electric power
being transmitted from the central unit accompanying at least the address
and control signal, wherein at least the address and control signals
transmitted from the central unit are respectively formed by arranging
pulses alternately different in polarity, and substantially two trains of
the address and control signals equal in contents but different only in
the polarity are transmitted.
5. A system according to claim 4 wherein a predetermined voltage signal of
one polarity is transmitted from the central unit also during the
transmission of the response signal and thereafter another voltage signal
of the same magnitude as but of the opposite polarity to said
predetermined voltage signal is transmitted so that a circuit of the
respective terminal units is short-circuited and opened and thereby the
response signal is transmitted from the terminal units.
6. A system according to claim 5 wherein the electric power included in the
signals transmitted from the central unit is accumulated in the power
accumulating means in the respective terminal units by means of a
full-wave rectification, and the address, control and the like signals
included in said transmitted signals are provided to following circuits
without being subjected to the full-wave rectification.
7. In a time division multiplex transmission apparatus comprising a central
unit and a plurality of terminal units respectively connected to said
central unit through a pair of bus lines, address and control signals
respectively corresponding to said terminal units being transmitted
sequentially in series from the central unit to the respective terminal
units, and response signals being transmitted from the respective terminal
units during periods between the preceding control signals and the
following address signals; an arrangement in which said central unit
comprises
(a) a clock pulse generating circuit,
(b) a synchronizing signal circuit which receives output pulses from said
clock pulse generating circuit,
(c) a start pulse generator which receives a first output signal from said
synchronizing signal circuit to generate a start pulse,
(d) an address selecting circuit which receives a second output signal from
the synchronizing signal circuit to select addresses,
(e) an address signal generating circuit which generates address signals
from an output signal of said address selecting circuit responsive to a
third output signal of the synchronizing signal circuit,
(f) a decoder for decoding the output signal of the address selecting
circuit,
(g) an instruction setting circuit for setting instructions for the
terminal units,
(h) an instruction reading circuit for reading contents of said instruction
setting circuit which are corresponding to the addresses decoded by said
decoder,
(i) a control signal generating circuit for generating control signals
depending on the contents read by said instruction reading circuit in
response to a fourth output signal of the synchronizing signal circuit,
(j) a signal summing circuit for arranging said start pulses, address
signals and control signals in a predetermined order responsive to a fifth
output signal of the synchronizing signal circuit,
(k) a combining circuit for providing output signals of said signal summing
circuit to the bus lines and receiving through the bus lines said response
signals from the terminal units,
(l) indicating circuits corresponding to the terminal units, and
(m) a driving circuit for driving said indicating circuits depending on the
contents of the response signals received by said combining circuit;
and said terminal units respectively comprise
(a') a combining circuit for receiving the start pulses, address signals
and control signals transmitted from said central unit through the bus
lines,
(b') an address register for storing the address signals,
(c') a control register for storing the control signals,
(d') a discriminating circuit for comparing the contents of the address
signals stored in said address register with a preliminarily set address
in this discriminating circuit to detect any coincidence between them,
(e') an address coincidence memory for storing any coincidence detected by
the discriminating circuit,
(f') a driving circuit connected to said control register and address
coincidence memory to be actuated responsive to an output signal of the
address coincidence memory and in accordance with the control signals
stored in the control register,
(g') an operating circuit operated by said driving circuit, and
(h') a detecting circuit for detecting operating states of said operating
circuit and transmitting a response signal depending on a detecting state
of the operating circuit to the bus lines through the combining circuit in
the terminal unit. |
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Claims |
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Description |
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This invention relates to time division multiplex transmission systems and,
more particularly, to improvements in time division multiplex transmission
systems wherein address, control and the like signals are transmitted from
a central control unit to a plurality of terminal units to operate them.
In this kind of conventional time division multiplex transmission systems,
a pair of electric power feeding lines and another pair of signal
transmitting lines have been provided between the central unit and the
respective terminal units. However, with such arrangement, there have been
difficulties in that the wiring is complicated and that a miswiring is
likely to be made and further the material and cost have not been able to
be reduced.
Alternatively a pair of transmission lines have been arranged between the
central unit and the respective terminal units and, further, modulators
and demodulators have been inserted between the central unit and the said
transmission lines and between the respective terminal units and the
transmission lines so that the address, control, response and the like
signals have been superposed on electric power waves to be transmitted
between the central unit and the respective terminal units. However, with
this arrangement, the modulators and demodulators have been required, the
system formation has been complicated and the cost reduction has not been
able to be attained.
In a further example, a pair of transmission lines have been provided
between the central unit and the respective terminal units so that
electric power has been respectively independently fed to the central unit
and to the respective terminal units. In this case, an electric power
source has been independently required for each of the terminal units and,
therefore, the cost reduction has been also unable to be attained. p The
present invention has been suggested to solve such defects as described
above by accumulating in the respective terminal units an electric power
accompanying at least the address and control signals time divisionally
transmitted out of the central control unit and obtaining required
electric power for operating the respective terminal units with the thus
accumulated electric power.
A primary object of the present invention is, therefore, to provide a time
division multiplex transmission system wherein a pair of transmission
lines are provided between a central control unit and a plurality of
terminal units so that each terminal unit receives and accumulates therein
an electric power accompanying such signal as address, control and the
like signals transmitted from the central unit to the respective terminal
units and such received and accumulated electric power in each terminal
unit is utilized as required power for the operation of the terminal unit.
Another object of the present invention is, secondly, to provide a time
division multiplex transmission system which is adapted to constantly
continuously transmit a predetermined voltage from a central control unit
to a plurality of terminal units so as to improve the electric power
supply to the respective terminal units.
A further object of the present invention is, thirdly, to provide a time
division multiplex transmission system wherein a predetermined electric
power is fed from a central control unit to a plurality of terminal units
at the time of transmitting response signals from the respective terminal
units to the central unit to have the response signals transmitted with
current signals, whereby the electric power supply at the time of
transmitting the response signals in the respective terminal units is
improved and the response signals are well attained.
A yet further object of the present invention is to provide a time division
multiplex transmission system wherein address, control and the like
signals transmitted from a central control unit to a plurality of terminal
units are provided with a predetermined symmetry in multiple polarities so
as to elevate the freedom of the wiring between the central unit and the
respective terminal units with respect to signal and power transmission
lines.
Other objects and advantages of the present invention shall become clear
upon reading the following explanation of the invention detailed with
reference to certain preferred embodiments shown in accompanying drawings,
in which:
FIGS. 1 and 2 are signal wave form diagrams showing a first embodiment of
the time division multiplex transmission system according to the present
invention, in the form of two aspects of a signal S.sub.i allotted to the
i-th terminal unit within a signal S present in the transmission lines;
FIG. 3 is a signal wave form diagram as a second embodiment of the present
invention, wherein a reverse polarized direct current voltage is
superposed on a signal
##EQU1##
in the signal S.sub.i of the first embodiment, specifically in the aspect
of FIG. 2;
FIG. 4 is a signal wave form diagram of a third embodiment of the present
invention, wherein a normally polarized direct current voltage is
superposed on the signal S.sub.i in the first embodiment of the aspect of
FIG. 2;
FIG. 5 is a similar diagram of a fourth embodiment of the present invention
wherein, in the period of transmitting a response signal to the central
unit from the i-th terminal unit in the signal S.sub.i, a voltage signal
R.sub.i of the same polarity as the signal P.sub.ij, P.sub.ij' is fed from
the central unit to the terminal unit so as to form the response signal
with a current signal;
FIG. 6 is also a similar diagram of a fifth embodiment of the present
invention wherein a voltage fed from the central unit to the terminal unit
during the period of transmitting the response signal in the fourth
embodiment shown in FIG. 5 is individually given to each signal Q.sub.ij'
in the particular response signal;
FIG. 7 is a further similar diagram of a sixth embodiment of the present
invention wherein, even during the period of transmitting the response
signal from the terminal unit to the central unit in the second embodiment
shown in FIG. 3, a direct current voltage of the polarity reverse to the
signal P.sub.ij' P.sub.ij' is fed from the central unit to the terminal
unit so as to form the response signal with a current signal;
FIG. 8 is another similar diagram of a seventh embodiment of the present
invention wherein, in the first embodiment shown in FIG. 2, another signal
P.sub.ij * which is of the reverse polarity to the signal P.sub.ij and is
the same in the magnitude is arranged between the signal P.sub.ij and
P.sub.ij+1 transmitted from the central unit to the terminal unit and
another signal P.sub.ij' * which is reverse polarized to but of the same
magnitude as the signal P.sub.ij' is disposed between the signals
P.sub.ij' and P.sub.ij'+1 on the same line;
FIG. 9 is also another similar diagram of an eighth embodiment of the
present invention wherein, in the seventh embodiment shown in FIG. 8 and
during the period of transmitting the response signal from the terminal
unit to the central unit in the signal S.sub.i, a voltage signal R.sub.i
of the same polarity as the signal P.sub.ij' P.sub.ij' and a voltage
signal R.sub.i * reverse polarized but of the same magnitude as the
voltage signal R.sub.i are fed from the central unit to the terminal unit
so as to form the response signal with a current signal;
FIG. 10 is a block diagram showing a basic wiring between a central control
unit A and a plurality of terminal units B.sub.i (i = 1, 2, . . . l) to
which the first to eighth embodiments of the present invention are
applicable;
FIG. 11 is a block diagram showing an example of circuit formation of the
central control unit A employed in the diagram of FIG. 10;
FIG. 12 is a block diagram showing an example of circuit arrangement of the
terminal unit B.sub.i in FIG. 10;
FIG. 13 is a circuit diagram showing an embodiment of combining circuit 11
in the central unit A of FIG. 11, in which other parts of the unit are
indicated by a block M;
FIG. 14A is a circuit diagram showing an embodiment of a receiving circuit
part of combining circuit 19.sub.i in the terminal unit shown in FIG. 12,
in which other parts of the unit are indicated by a block N';
FIG. 14B is a circuit diagram showing more in detail the combining circuit
19.sub.i of FIG. 14A as associated with an operating circuit 27.sub.i of
the terminal unit in FIG. 12, with other parts of the unit indicated by a
block N', which is adapted to transmit responsive signals as a voltage
signal;
FIG. 14C is a circuit diagram similar to FIG. 14B and showing the combining
circuit 19.sub.i with the operating circuit 27.sub.i shown in FIG. 14B as
adapted to transmit the responsive signal as a current signal;
FIG. 15 is a circuit diagram showing another embodiment of the combining
circuit 11 in the central unit A of FIG. 11, which is adapted to transmit
signals different from those in the case of FIG. 13;
FIG. 16A is a circuit diagram showing a further embodiment of the combining
circuit 19.sub.i in the terminal unit B.sub.i of FIG. 12, which is
controllable even with signals different from those in the case of FIG.
14A;
FIG. 16B is a circuit diagram showing more in detail the combining circuit
19.sub.i of FIG. 16A as associated with the operating circuit 27.sub.i,
with other parts of the terminal unit indicated by a block N', which is
adapted to transmit the responsive signals as a voltage signal;
FIG. 16C is a circuit diagram similar to FIG. 16B and showing the combining
circuit 19.sub.i with the operating circuit 27.sub.i of FIG. 16B as
adapted to transmit the responsive signal as a current signal;
FIG. 17 is a circuit diagram showing a further embodiment of the combining
circuit 11 in the central unit A of FIG. 11, which is adapted to transmit
signals different from those in the cases of FIGS. 13 and 15;
FIG. 18 is a circuit diagram showing yet another embodiment of the
combining circuit 11 in the central unit A of FIG. 11, which is adapted to
transmit siganls different from those in the cases of FIGS. 13, 15 and 17;
FIG. 19 is a circuit diagram showing a further embodiment of the combining
circuit 19.sub.i in the terminal unit B.sub.i of FIG. 12, of which
connection wiring to the transmission bus lines can be made optionally as
being different from the cases of FIGS. 14 and 16;
FIGS. 20A and 20B show jointly a circuit diagram of another practical
embodiment of the central unit A shown in FIG. 11, which is adapted to be
operated with the signal shown in FIG. 5; and
FIG. 21 is a circuit diagram showing another practical embodiment of the
terminal unit B.sub.i shown in FIG. 12, which is adapted to be operated
with the signal shown in FIG. 5.
Referring now to FIG. 10, the signal S appears in the bus lines connecting
between the central unit A and the respective terminal units B.sub.i (i =
1, 2, . . . l) in a predetermined cycle. This signal S comprises a signal
S.sub.i allotted to the i-th terminal unit B.sub.i, whereas the signal
S.sub.i comprises generally a signal P.sub.ij, P.sub.ij' (j = 0, 1, 2, . .
. k, j' = 1, 2, . . . , mi) transmitted from the central unit A to the
terminal unit B.sub.i and a signal Q.sub.ij' (j' = 1, 2, . . . mi)
transmitted from the terminal unit B.sub.i to the central unit A.
The operation of the circuit in FIG. 10 employed in the system according to
the present invention shall be referred briefly with reference to FIGS. 11
and 12.
In the central control unit A of FIG. 11, an output pulse from a clock
pulse generating circuit 1 is provided to a synchronizing signal circuit
2, and an output of this circuit 2 is presented to a starting pulse
generating circuit 3, wherein the output is converted to a starting pulse
P.sub.i,o (i = 1, 2, 3, . . . l) which is provided to a signal summing
circuit 4. Another output of the synchronizing signal circuit 2 is
provided, on the other hand, to an address selecting circuit 5 and this
circuit 5 presents signals indicating the first to l-th addresses in
sequence to an address signal generating circuit 6 comprising a shift
register and to a decoder 7 (the signals may be presented in any desired
order but, here, the addresses may be determined in the order of their
presentation from the circuit 5 and they are referred to as being
presented in sequence, while there may be of course lacking numbers). The
address signal generating circuit 6 receives the output of the
synchronizing signal circuit 2 as a clock pulse and provides address
signals
##EQU2##
(which shall be P.sub.i1 + P.sub.i2 + . . . + P.sub.ik and represent that
the respective signals are arranged in this order here and throughout the
following descriptions), which are presented to the signal summing circuit
4.
In the decoder 7 referred to above, the output signal accompanying the i-th
address from the address selecting circuit 5 is discriminated, an
instruction read circuit 8.sub.i for the i-th instruction is driven by the
thus discriminated output signal and contents of an instruction setting
circuit 9.sub.i corresponding to the i-th instruction read circuit 8.sub.i
are read out and presented to a control signal generating circuit 10
comprising a shift register. In the control signal generating circuit 10,
a control signal
##EQU3##
is provided in response to the contents of the instruction setting circuit
9.sub.i, which signal is presented to the signal summing circuit 4.
In this signal summing circuit 4, signals
##EQU4##
arranged in the order of the starting pulse address signal and the control
signal are prepared.
These output signals
##EQU5##
of the signal summing circuit 4 are properly adjusted as shown in FIGS. 1
to 9 in the summing circuit 11 and presented to the bus lines.
After the signals
##EQU6##
are sent out of the combining circuit 11 to the bus lines, a response
signal
##EQU7##
is transmitted to the combining circuit 11 through the bus lines from the
terminal unit B.sub.i.
The response signal Q.sub.ij' reaching the combining circuit 11 causes
gating in a gate circuit 12 with the output signal of the synchronizing
signal circuit 2 so as to receive signals only coming in during the gate
opening period and to present the signal Q.sub.ij' to a clock pulse
generating circuit 13, so that a clock pulse which rises in response to
the rise of the response signal Q.sub.ij' will be generated. In a pulse
width detecting circuit 14, the pulse width of the response signal
Q.sub.ij' caused to reach the gate circuit 12 by the output pulse of the
clock pulse generating circuit 13 is detected and the response signal
Q.sub.ij' is read in turn into a display driving signal generating circuit
15 including a shift register in accordance with the detected width of the
signal.
The display driving signal generating circuit 15 properly retains a display
retaining circuit 16.sub.i in response to the response signals
##EQU8##
in order to retain the display retaining circuit 16.sub.i, at this time,
there will be necessary a signal given through a gate circuit 17.sub.i in
case the output of the synchronizing signal circuit 2 and the output of
the decoder 7 are present simultaneously. The display retaining circuit
16.sub.i drives a succeeding display circuit 18.sub.i and displays the
contents of each response signal Q.sub.ij' of the response signal
##EQU9##
by means of lamps or the like.
After the response signal
##EQU10##
is received, the above described operation is again repeated,
##EQU11##
is transmitted to a terminal unit B.sub.i+1 and the response signal
##EQU12##
is received.
In the terminal unit B.sub.i in FIG. 12, the signal
##EQU13##
is transmitted to a combining circuit 19.sub.i through the bus lines from
the central control unit A. Another succeeding clock pulse generating
circuit 20.sub.i is driven so that a clock pulse rising in response to the
rise of the signals P.sub.ij and P.sub.ij' will be generated by the output
of the combining circuit 19.sub.i. In a pulse width detecting circuit
21.sub.i, the pulse widths of the signals P.sub.ij and P.sub.ij' caused to
reach the combining circuit 19.sub.i by the output pulses of the clock
pulse generating circuit 20.sub.i are detected and, in accordance with the
pulse widths of the signals P.sub.ij and P.sub.ij', the signals P.sub.ij
and P.sub.ij' are read in turn respectively into an address register
22.sub.i and control register 23.sub.i.
The address signal
##EQU14##
thus stored in the address register 22.sub.i is compared with addresses
set in a discriminating circuit 24.sub.i and, in case it coincides, such
address coincidence is stored in an address coincidence memory 25.sub.i.
When the signals of which addresses are coinciding reach the address
coincidence memory 25.sub.i, a driving circuit 26.sub.i is driven in
response to the control signal
##EQU15##
stored in the control register 23.sub.i. By the thus driven circuit
26.sub.i, an operating circuit 27.sub.i including relays or the like is
operated. The state of this operating circuit 27.sub.i or other state to
be watched or detected is detected with a detecting circuit 28.sub.i and
the signal
##EQU16##
is prepared and provided to the bus lines through the combining circuit
19.sub.i.
Therefore, the signal
##EQU17##
transmitted from the central unit A to the terminal unit B.sub.i and the
signal
##EQU18##
transmitted from the terminal unit B.sub.i to the central unit A appear in
this order in the bus lines and the signal S.sub.i for the i-th address is
formed. The signal
##EQU19##
is sent out to the bus lines in a predetermined cycle to watch and control
the terminal unit B.sub.i at all times.
The arrangement, operation and effect in the case of controlling and
watching a plurality of the terminal units B.sub.i with the central
control unit A in FIG. 10 using the respective signals S.sub.i shown in
FIGS. 1 through 9 shall be detailed in the following.
First of all, the case of utilizing the signal S.sub.i shown in FIG. 1
shall be referred to. In this case, the central control unit A is formed
as shown in FIG. 13, and the signal receiving part and power accumulating
part of the terminal unit B.sub.i are formed as shown in FIG. 14.
In FIG. 13, when the output of the signal summing circuit 4 shown in FIG.
11 is given to the base of a transistor T.sub.1, for the high level of the
output, the transistor T.sub.1 will be made ON, transistors T.sub.2 and
T.sub.5 will be OFF and transistors T.sub.3 and T.sub.4 will be ON so that
a source voltage E will be applied across the bus lines but, on the other
hand, for the low level of the output of the circuit 4, the transistor
T.sub.1 will be made OFF, the transistors T.sub.2 and T.sub.5 will be ON,
the transistors T.sub.3 and T.sub.4 will be OFF and the source voltage E
will not be applied to the bus lines. Accordingly, the signal
##EQU20##
in the signals S.sub.i shown in FIG. 1 will be provided to the bus lines.
On the other hand, the signal
##EQU21##
transmitted from the terminal unit B.sub.i will be properly divided by
resistances R.sub.1 and R.sub.2 inserted in series between the respective
bus lines and will then be given to the gate circuit 12 in FIG. 11.
In FIG. 14A, when the signal
##EQU22##
reaches the combining circuit 19.sub.i in the terminal unit from the
central unit A through the bus lines, a condenser C.sub.i1 will be charged
through a circuit of the resistance R.sub.i1, diode D.sub.i1 and
resistance R.sub.i2. The electric power with which the condenser C.sub.i1
is charged will be fed to the clock pulse generating circuit 20.sub.i,
pulse width detecting circuit 21.sub.i and so on in the arrangement of
FIG. 12.
A series circuit of resistances R.sub.i3 and R.sub.i4 is inserted between
the respective bus lines through the resistance R.sub.i1 and the voltage
at the connecting point of these resistances R.sub.i3 and R.sub.i4 is
given to the clock pulse generating circuit 20.sub.i, control register
23.sub.i and address register 22.sub.i shown in FIG. 12, through a
resistance R.sub.i5.
By the signal
##EQU23##
transmitted through the bus lines from the central unit A to the terminal
unit B.sub.i among the signals S.sub.i shown in FIG. 1, the electric power
required for operating the terminal unit B.sub.i can be also transmitted.
More detailed structure and operation of the terminal unit B.sub.i in the
case where the same is adapted to transmit the responsive signal as a
voltage signal as shown in FIG. 1 shall now be referred to with reference
to FIG. 14B.
In FIG. 14B, as the signal
##STR1##
from the central unit A reaches the combining circuit 19.sub.i of the
terminal unit B.sub.i through the bus lines, the charge of the condenser
C.sub.i1 is performed through the circuit of the resistance R.sub.i1,
diode D.sub.i1 and resistance R.sub.i2 and, further, a condenser C.sub.i2
included in the circuit 19.sub.i is also charged through a circuit of the
resistance R.sub.i1, diode D.sub.i2 and resistance R.sub.i6.
The signal
##EQU24##
is also provided to the address register 22.sub.i and control register
23.sub.i shown in FIG. 12 through a resistance R.sub.i5 as voltage-divided
by the series connected resistances R.sub.i3 and R.sub.i4, after passing
through the resistance R.sub.i1. The signal component
##EQU25##
provided to the address register 22.sub.i is compared with the set address
in the discriminating circuit 24.sub.i and, in the event of a coincidence
therewith, the address coincidence is stored in the address coincidence
memory 25.sub.i. When such address coincidence is stored in the memory
25.sub.i contents in the control register 23.sub.i are provided through
the driving circuit 26.sub.i to the transistor T.sub.i1 or T.sub.i2 in the
operating circuit 27.sub.i so that the transistor will be made ON. Upon
such ON operation of the transistor T.sub.i1 or T.sub.i2, a coil L.sub.1
or L.sub.2 for making an associated latching relay or the like (not shown)
is excited, whereby the latching relay is actuated.
The state of the latching relay is detected by the detecting circuit
28.sub.i and, depending on the detected state, a transistor T.sub.i3 and
sequentially a transistor T.sub.i4 included in the circuit 19.sub.i are
conducted to be ON, so that the charged voltage in the condenser C.sub.i2
is applied to the bus lines through the transistor T.sub.i4, a resistance
R.sub.i7 connected to the emitter of the transistor T.sub.i4 and further
through the resistance R.sub.i1 and thereby the response signal can be
transmitted to the bus lines as the voltage signal.
Here, among the signals S.sub.i shown in FIG. 1, the response signal
Q.sub.ij' will gradually reduce in the magnitude with the discharge of the
condenser C.sub.i1 as seen in the drawing, undesirably. In order to
prevent such reduction of the response signal Q.sub.ij', the magnitude of
the response signal Q.sub.ij' may be taken properly to be so small as not
to be influenced by the discharge of the condenser C.sub.i1 as shown in
FIG. 2 but, in this case, there remains a problem that practical handling
of the system becomes somewhat uneasy.
In the present invention, in order to eliminate such problems as above of
the embodiment shown in FIGS. 1 and 2, there is employed a transmission
system wherein, as shown in FIGS. 3 and 4, a predetermined voltage is
applied to the bus lines by the central unit A at least during the period
of transmitting the signals from the central unit A to the terminal units
B.sub.i.
These embodiments of FIGS. 3 and 4 shall be detailed respectively in the
followings.
In the case of using such signal as shown in FIG. 3, the central unit A is
formed as shown in FIG. 15 and the terminal unit B.sub.i is formed as
shown in FIG. 16.
In FIG. 15, when the output of the signal summing circuit 4 as in FIG. 11
is on a low level, the output is given to the emitter of a transistor
T.sub.1 through a diode D.sub.1. In this case, a sufficient voltage
difference between the emitter and the base of the transistor cannot be
secured and the transistor T.sub.1 will be OFF so that a further
transistor T.sub.2 will be also OFF, but transistors T.sub.3, T.sub.4 and
T.sub.5 will be ON, whereas further transistors T.sub.6 and T.sub.7 will
be OFF. Accordingly a source voltage E.sub.2 will be applied across the
bus lines. On the other hand, when the output of the signal summing
circuit 4 is on a high level, the transistors T.sub.1 and T.sub.2 will be
ON, the transistors T.sub.3, T.sub.4 and T.sub.5 will be OFF, the
transistors T.sub.6 and T.sub.7 will be ON and, therefore, a source
voltage E.sub.1 will be applied across the bus lines. At this time, as the
direction of applying the source voltage E.sub.2 and that of applying the
source voltage E.sub.1 are reverse to each other,
##EQU26##
of the signals shown in FIG. 3 will be transmitted from the central unit A
to the terminal unit B.sub.i.
When the response signal
##EQU27##
is to be received, as the signal sent from the synchronizing signal
circuit 2 to the gate circuit 12 is given to the emitter of the transistor
T.sub.1 through the diode D.sub.2 and further to the base of the
transistor T.sub.8, the transistors T.sub.1 and T.sub.2 will be ON, the
transistors T.sub.3, T.sub.4, T.sub.5, T.sub.6 and T.sub.7 will be OFF and
the transistor T.sub.8 will be ON. Therefore, the response signal
Q.sub.ij' transmitted through the bus lines will be properly divided by
the resistances R.sub.1 and R.sub.2 inserted between the bus lines and
will be given to the gate circuit 12.
In FIG. 16, a diode bridge BG.sub.i is inserted between the bus lines
through the resistance R.sub.i1, a series circuit of the resistance
R.sub.i2 and condenser C.sub.i1 is inserted between the output ends of the
diode bridge BG.sub.i, and the electric power of the signal
##EQU28##
transmitted from the central unit A to the condenser C.sub.i1 is charged
therein. The electric power with which the condenser C.sub.i1 is charged
is given to each part of the terminal unit B.sub.i in the same manner as
in FIG. 14. A series circuit of resistances R.sub.i3 and R.sub.i4 is
connected at one end with one of the input terminals of the diode bridge
BG.sub.i and at the other end with the other one of the output terminals
of the diode bridge BG.sub.i. The voltage of the connecting point of the
resistances R.sub.i3 and R.sub.i4 is given to the clock pulse generating
circuit 20.sub.i, control register 23.sub.i and address register 22.sub.i
through the resistance R.sub.i5. Therefore, the signal
##EQU29##
will be provided to the clock pulse generating circuit 20.sub.i, control
register 23.sub.i and address register 22.sub.i through the series circuit
of the resistances R.sub.i3 and R.sub.i4 and the resistance R.sub.i5.
As a predetermined voltage of the reverse polarity is superposed on the
signal
##EQU30##
transmitted from the central unit A to the terminal unit B.sub.i through
the bus lines among the signals S.sub.i shown in FIG. 3, a sufficient
amount of the charge in the condenser C.sub.i1 in the terminal unit
B.sub.i can be well secured, the voltage of the condenser C.sub.i1 can be
maintained at a value high enough during the period of providing and
transmitting the response signal Q.sub.ij' back to the central unit A from
the terminal unit B.sub.1 and thus the response signal Q.sub.ij' can be
made larger.
If, in the above, the magnitude of the predetermined voltage is set to be
larger than that of an actually required voltage, the electric power
obtained in the terminal unit B.sub.i by the signal
##EQU31##
transmitted to the terminal unit B.sub.i from the central unit A can be
used for driving the terminal unit B.sub.i only during the period of
sending the response signal
##EQU32##
out of the terminal unit B.sub.i to the central unit A and also to form
the response signal Q.sub.ij'. Therefore, the response signal Q.sub.ij'
can be made much larger than in the case of the embodiments shown in FIGS.
1 and 2.
In the above, additionally, the polarity of the predetermined voltage and
that of the signal
##EQU33##
may be the same.
References shall now be made to a case of utilizing the signal S.sub.i
shown in FIG. 4. In this case, the central unit A is formed as shown in
FIG. 17, while the terminal unit B.sub.i of the same structure as in FIG.
16 is used.
In the central unit of FIG. 17, when the output of the signal summing
circuit 4 is on the high level, the transistor T.sub.1 will be ON, whereas
the transistor T.sub.2 will be OFF and the source voltages E.sub.1 and
E.sub.2 will be applied across the bus lines. On the other hand, when the
output of the signal summing circuit 4 is on the low level, the transistor
T.sub.1 will be OFF whereas the transistor T.sub.2 will be ON and only the
source voltage E.sub.2 will be applied to the bus lines.
That is to say, during all the operation, a predetermined voltage is
applied to the bus lines from the central unit A, the signal
##EQU34##
of FIG. 14 is transmitted from the central unit A to the terminal unit
B.sub.i and then the response signal
##EQU35##
is transmitted back from the terminal unit B.sub.i to the central unit A.
The response signal Q.sub.ij' is divided by the resistances R.sub.1 and
R.sub.2 inserted between the bus lines and is given to the gate circuit
12.
With reference to the terminal unit, the foregoing descriptions on FIG. 16
should be referred to.
Now, as a predetermined voltage is applied by the central unit A to the
terminal unit B.sub.i at all times during the operation as shown by the
signal S.sub.i of FIG. 4, if the magnitude of the predetermined voltage is
set to be above the voltage actually required for the terminal unit
B.sub.i, the electric power obtained in the terminal unit B.sub.i
depending on the signal
##EQU36##
transmitted from the central unit A to the terminal unit B.sub.i can be
used only to form the response signal
##EQU37##
and the magnitude of the response signal can be secured sufficiently as
compared with the embodiments of FIGS. 1 to 3.
Considering here the embodiments in FIGS. 1 to 4, it is found that there
still remains a fear that, in case the bus lines are of extensive length,
the response signal transmitted from the terminal unit B.sub.i to the
central unit A will become feeble. In order to eliminate this fear,
further, the present invention adopts a system wherein, as shown in FIGS.
5 to 7, at least during the period of transmitting the response signal
from the terminal unit B.sub.i to the central unit A, a predetermined
voltage is applied to the bus lines by the central unit A and the signal
from the terminal unit B.sub.i to the central unit A is transmitted in the
form of a current signal. The respective embodiments of FIGS. 5 to 7 shall
be referred to in turn in the following.
In the case of utilizing the signal S.sub.i shown in FIG. 5, the central
unit A is formed as shown in FIG. 13 and the terminal unit B.sub.i is
formed as shown in FIG. 14A, basically. In these drawings, other parts
than those illustrated are indicated by a block M or N, for details of
which FIG. 11 or 12 should be referred to.
In FIG. 13, the base of the transistor T.sub.1 is connected to the output
terminal of the signal summing circuit 4 through a diode and is further
connected through another diode to the output terminal of a synchronizing
signal circuit 2 connected to a gate circuit 12. Thus, when a high level
signal enters the base of the transistor T.sub.i, the transistor T.sub.i
will be ON, the transistor T.sub.2 will be OFF, and the transistors
T.sub.3, T.sub.4 and T.sub.5 will be ON, so that a source voltage E will
be impressed between the bus lines and thereby the signal
##EQU38##
shown in FIG. 5 will be transmitted to the terminal unit B.sub.i.
On the other hand, in the terminal unit B.sub.i shown in FIG. 14A, the
response signal Q.sub.ij' (j' = 1, . . . mi) is produced by properly
short-circuiting the bus lines with the detecting circuit 28.sub.i. In the
central unit A, the connecting point of the resistances R.sub.1 and
R.sub.2 inserted between the bus lines may be connected to the input
terminal of the gate circuit 12 through an inverter.
The signal
##EQU39##
shown in FIG. 5 is sent out of the central unit A to the bus lines, the
condenser C.sub.i1 is charged with such electric power accompanying | | |
