 |
Description  |
|
|
BACKGROUND OF THE INVENTION
This invention relates to analog signal processing devices, and more
particularly, to electronic filtering and mixing devices. This invention
further relates to the transceiver and components thereof described and
claimed in the following U.S. Patent Applications filed of even date with
and assigned to the assignee of the present invention: U.S. Ser. No.
791,611 entitled "A Digitally Transmitting Transceiver" by Edward R.
Caudel and William R. Wilson; U.S. Ser. No. 791,629 entitled "A Clarifying
Radio Receiver" by Michael J. Cochran and Edward R. Caudel; U.S. Ser. No.
791,449 entitled "An Automatically Clarifying Radio Receiver" by Michael
J. Cochran and Edward R. Caudel; U.S. Ser. No. 791,254 entitled "A
Computer Controlled Radio System" by Michael J. Cochran and Edward R.
Caudel; U.S. Ser. No. 791,450 entitled "A Transceiver With Only One
Reference Frequency" by Michael J. Cochran; U.S. Ser. No. 791,264 entitled
"An Electronic Phase Locked Loop" by Michael J. Cochran; U.S. Ser. No.
791,265 entitled "A Signal Strength Measuring Transceiver" by Edward R.
Caudel; U.S. Ser. No. 791,614 entitled " A Charge Transfer Device Radio
System" by Michael J. Cochran; U.S. Ser. No. 791,253 entitled "A
Transceiver Capable of Sensing A Clear Channel" by Jerry D. Merryman,
Michael J. Cochran and Edward R. Caudel; U.S. Ser. No. 791,256 entitled "A
Highly Selective Programmable Filter Module" by Michael J. Cochran and
Edward R. Caudel; and U.S. Ser. No. 791,616 entitled "A Dual Processor
Transceiver" by Edward R. Caudel, William R. Wilson and Thomas E. Merrow.
Such copending patent applications are hereby incorporated herein by
reference. Filtering devices receive electronic input signals comprised of
a plurality of non-overlapping frequency bands, and filter a selected band
from the plurality. Mixing devices receive frequency signals of one
frequency spectrum, and generate output signals having a frequency
spectrum proportional to the input signals, but shifted in frequency.
The invention herein described is called a highly selective programmable
filter module because it has passbands whose width and center frequency
are adjustable in very small increments. Applications for this type of
filtering capability are very broad. Typical uses include the processing
of signals in radio systems, television receivers, and CB transceivers. As
an example of an application for the variable bandwidth feature, some
radio receivers demodulate both amplitude modulated signals (AM) and
single sideband signals (SSB). The bandwidth of an AM signal is
approximately twice the bandwidth of an SSB signal. Therefore, during one
time interval, such receivers require a filter having a bandwidth of an AM
signal; and alternatively, during another time interval, require a filter
having a bandwidth of an SSB signal. The invention herein described has a
bandwidth which is selectively adjustable to the width of an AM signal or
an SSB signal.
In the above example, the passband width of the invention would be varied
by a factor of approximately 2:1. Alternatively, the invention herein
described provides passbands with widths which are selectable in much
smaller increments. As an example, the width of a 10-kHz bandpass may be
increased or decreased in increments of only 5 Hz.
As mentioned above, the invention herein described also has passbands whose
center frequency is adjustable in very small frequency increments. This
capability may be utilized in a CB transceiver, for example, to filter one
band of signals from a plurality of non-overlapping frequency bands. In
this application, the center frequency of the filter's passband is
adjusted in increments equal to the spacing between adjacent channels.
Typically, single sideband channels are separated by approximately 5 kHz;
whereas, AM channels are separated by approximately 10 kHz. The invention
herein described is capable of performing frequency band shifting for
filtering both AM and SSB channels. Additionally, the invention herein
described is capable of frequency shifting its center frequency in
increments much smaller than adjacent channel spacing. For example, a
passband of approximately 5-kHz width may be shifted in increments of 10
Hz by the invention herein described.
In addition to performing a filtering operation, the present invention
performs a mixing operation; and, the frequency at which the signals are
mixed is also adjustable by very small frequency increments. This
capability, in combination with the capability to vary the center
frequency of a passband by small increments, may be utilized to perform a
clarifying function, as an example. The clarifying function is performed
on single sideband signals. Such signals are difficult to demodulate
because a sideband may lie anywhere within its assigned frequency channel.
As a result, audible tones which are produced by demodulating a sideband
channel have either higher frequency components or lower frequency
components than should be present dependent upon whether the sideband lies
in the upper portion or the lower portion of its assigned channel,
respectively. The present invention may be utilized to clarify the
resulting audible sound by adjusting the center frequency of its passband
to be precisely aligned with the sideband signals regardless of where they
lie within a channel. As a result of this precise alignment, the single
sideband will be filtered and mixed by a frequency which will compensate
for any misalignment of the sideband in the channel.
The above application of the invention are herein given only as examples.
The invention has a multitude of applications. and can be applied wherever
the bandwidth of a filter is required to be highly selectable, the center
frequency of a filter is required to be highly adjustable, or a mixing
device is required for shifting an input signal by a highly selectable
frequency.
Accordingly, it is one object of the invention to provide an improved
electronic filtering device.
It is another object of the invention to provide a filter having passbands
with a highly selectable bandwidth.
Another object of the invention is to provide a filter having passbands
with a center frequency which are adjustable by fine increments.
Another object of the invention is to provide a mixing device for frequency
shifting an input signal by a finely adjustable frequency.
Still another object of the invention is to provide a filter module having
passbands and a center frequency which are proportional to a variable
reference frequency times the term (N1/N2) N1 and N2 are arbitrary
integers.
SUMMARY OF THE INVENTION
These and other objects are accomplished in accordance with the invention
by a filter module comprised of a phase locked loop and a charge transfer
device bandpass filter. The bandpass filter has a clocking input coupled
to receive clocking signals of a selectable frequency f.sub.S. The filter
has passbands centered at frequencies N .times. f.sub.S .+-.Kf.sub.O. The
phase locked loop has an input coupled to receive a reference clock signal
of a variable frequency f.sub.R. In response thereto, the phase locked
loop generates a clocking frequency of the form f.sub.R .times. N1. This
signal is received by a divide-by N2 counter. The output of the counter
couples to the clocking input of the transversal filter. N1 and N2 are
arbitrary integers.
DESCRIPTION OF THE DRAWINGS
The essential features believed to be characteristic of the invention are
set forth in the appended claims; the invention itself, however, as well
as other features and advantages thereof, may best be understood by
referring to the following detailed description of the preferred
embodiments when read in conjunction with the accompanying drawings;
wherein:
FIG. 1 is a block diagram illustrating the major components of a
transceiver constructed according to the invention.
FIG. 2 is a more detailed block diagram of the transceiver of FIG. 1
wherein the receive signal path components are emphasized.
FIGS. 3A-3K are a set of frequency diagrams illustrating signals in the
frequency domain which are present at various points on the receive signal
path of FIG. 2.
FIG. 4 is a detailed circuit diagram of CCD filter 700 in signal path of
FIG. 2.
FIG. 5 is detailed circuit diagram of a clocking module 3000 included
within FIG. 2.
FIGS. 6A-6F are detailed circuit diagrams of a clocking module 3100
included within FIG. 2.
FIGS. 7A-7C are detailed logic diagrams of a clocking module 3200 included
within FIG. 2.
FIG. 8 is a circuit diagram illustrating the source of logic signals which
are utilized by clocking modules 3000- 3200.
FIG. 9 is a circuit diagram identical to FIG. 2 with the exception that the
transmit signal path components are emphasized rather than the receive
signal path components.
FIGS. 10A-10K are a series of frequency diagrams illustrating signals at
various points on the transmit signal path of FIG. 9.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
Referring now to FIG. 1, a block diagram illustrating the major components
of a transceiver which is constructed according to the invention is
illustrated. The transceiver is comprised of an antenna 10, a signal
processing unit 20, a speaker 30, a control unit 40, and a power terminal
50. These components are electrically intercoupled by conductive cables
61-64 as illustrated in FIG. 1.
The transceiver of FIG. 1 has a transmit mode of operation and a receive
mode of operation. Basically, in the transmit mode the operator speaks
into a microphone 41 contained in control unit 40, and the audio signals
are therein converted to electrical signals which are sent to analog
signal processor 20 over cables 63 and 64. Signal processor 20 frequency
shifts the received signal from an audio frequency to a frequency band of
a selectable high frequency channel. The selected channel may be either a
single sideband channel of approximately 5-kHz bandwidth, or an amplitude
modulated channel of approximately 10 kHz. In either case the frequency
shifted signals are sent via cable 61 to antenna 10 and therein
transmitted via radiation.
In the receive mode, antenna 10 receives radiated electrical signals
comprised of a plurality of frequency bands lying respectively within a
plurality of non-overlapping frequency channels. The plurality of
frequency bands are sent to signal processor 20 via cable 61. Signal
processor 20 filters a selectable band from the plurality of bands, and
down shifts in frequency the selected band to an audible frequency range.
The selected down shifted frequency band is sent to speaker 30 via cable
64 where it is therein converted to audible sounds.
The manner in which the transceiver of FIG. 1 performs the above described
receive operation is best understood by referring to FIG. 2 and FIG. 3.
FIG. 2 is a circuit diagram of the transceiver of FIG. 1. The circuit
includes a signal path which is operable in the receive mode and which is
emphasized in FIG. 2 by a thickened line. Signals S1-S12 are present at
various points (as illustrated in FIG. 2) on this signal path. FIG. 3 is a
set of frequency diagrams illustrating some of the signals S1-S12 in the
frequency domain.
Antenna 10 is the first element of the receive signal path. Cable 61
couples to the output of antenna 10 and signal S1 as illustrated in FIG.
3a is generated thereon. Basically, signal S1 is unfiltered and thus is
comprised of frequency components which cover the electromagnetic
spectrum. Lead 61 couples to filter 100. Filter 100 has an output lead 101
and signals S2 are generated thereon. As illustrated in FIG. 3b, signal S2
has a frequency range of approximately 26MHz to 28MHz. The skirt response
of filter 100 is not critical as its only function is to pass the band of
frequencies lying between 26.965MHz and 27.405MHz. This range of
frequencies includes 40 amplitude modulated (AM) channels as presently
assigned by the FCC. Table I lists the center frequency of each of the 40
channels. Each AM channel is divided into a lower sideband channel and an
upper sideband channel. FIG. 3b illustrates the 26.96MHz-27.405MHz
frequency range by the cross hatched areas S2a. FIG. 3B1 is a blow up of
area S2a and single sideband channels L1, U1, L2, U2, lying within the
first two AM channels are illustrated therein.
TABLE I
______________________________________
CENTER CENTER
CH FREQUENCY CH FREQUENCY
______________________________________
1 26.965 20 27.205
2 26.975 21 27.215
3 26.985 22 27.225
X 26.995 24 27.235
4 27.005 25 27.245
5 27.015 23 27.255
6 27.025 26 27.265
7 27.035 27 27.275
X 27.045 28 27.285
8 27.055 29 27.295
9 27.065 30 27.305
10 27.075 31 27.315
11 27.085 32 27.325
X 27.095 33 27.335
12 27.105 34 37.345
13 27.115 35 27.355
14 27.125 36 27.365
15 27.135 37 27.375
X 27.145 38 27.385
16 27.155 39 27.395
17 27.165 40 27.405
18 27.175
19 27.135
X 27.195
______________________________________
TABLE II
______________________________________
CH f.sub.s1 CH f.sub.s1
______________________________________
1 23.840 20 24.080
2 23.850 21 24.090
3 23.860 22 24.100
X 23.870 24 24.110
4 23.880 25 24.120
5 23.890 23 24.130
6 23.900 26 24.140
7 23.910 27 24.150
X 21.910 28 24.160
8 23.930 29 24.170
9 23.940 30 24.180
10 23.950 31 24.190
11 23.960 32 24.200
X 23.970 33 24.210
12 23.980 34 24.220
13 23.990 35 24.230
14 24.000 36 24.240
15 24.010 37 24.250
X 24.020 38 24.260
16 24.030 39 24.270
17 24.040 40 24.280
18 24.050
10 24.060
X 24.070
______________________________________
Lead 101 couples to the signal input of a mixer 200 which has an output
lead 201 and signals S3 are generated thereon. Mixer 200 also has an input
lead 202 for receiving clock signals of the first selectable frequency
f.sub.s1. The frequency f.sub.s1 is chosen to equal the difference between
the center frequency of the selected AM channel and the quantity 3.125
mHz. Mixer 200 generates signal S3 by mixing signal S2 with frequency
f.sub.s1, and thus the selected AM channel is centered at the frequency
3.125 MHz. This fact is illustrated in FIG. 3c. TABLE II lists the value
of frequency f.sub.s1 along side of the number of the selected AM channel.
Lead 201 couples to a second mixer 300. Mixer 300 has a clock input lead
301 and an output lead 302. A clocking signal of 3.58 MHz is applied to
lead 301. Mixer 300 mixes signals S3 with the signal on lead 301 and, in
response thereto, generates signals S4 on lead 302. As a result of the
mixing operation, the selected AM channel in S4 is centered at frequency
455 kHz. FIG. 3d illustrates signal S4.
Signal S4 passes through a noise blanker 400, and noise blanker 400 is
serially coupled to an amplifier 500. Signals S5 and S6 are generated by
noise blanker 400 and amplifier 500, respectively. In general, the
function of noise blanker 400 and amplifier 500 is to filter and amplify
signal S4, but not to frequency shift signal S4. Thus, the center
frequency of the selected channel is present in signal S6 at 455 kHz.
Signal S6 is illustrated in the frequency domain in FIG. 3e.
In the receive mode, a switch 600 couples signals S6 to the input of a
charge transfer device filter 700 via a lead 701. Charge transfer device
filter 700 also has a clocking lead 702 for receiving clocking signals of
a second selectable frequency f.sub.s2. In response to the frequency
f.sub.s2, filter 700 generates output signals S8 on a lead 703.
In the preferred embodiment, charge transfer device filter 700 is a charge
coupled device (CCD) transversal filter having a plurality of passbands
which are programmable by varying the selectable frequency f.sub.s2.
Copending application, Ser. No. 758,366, entitled, "Frequency Converting
Filter," by Jerry Norris and Clinton Hartmann, filed January, 1977,
assigned to the same assignee of this application, contains a detailed
description of its construction. Basically, the charge coupled device
transversal filter is comprised of a plurality of serially connected
stages having a split electrode structure defining an impulse response of
the form (sine N/N) (cosine 2.pi. f.sub.O N). In this expression, the
frequency f.sub.0 equals 1/(N.sub.0 .times. t.sub.s) where the quantity
1/t.sub.s equals the selectable frequency f.sub.S2, and N.sub.0 is the
number of stages over which the term cosine (2.pi. f.sub.O t) completes
one cycle. The bandwidth .DELTA.f of each of the passbands equals
1/(t.sub.s N.sub.1) where the quantity 1/t.sub.s again equals the
selectable sampling frequency f.sub.s2, and N.sub.1 equals the number of
stages in which the term (sine N)/N passes before reaching its first zero
crossing. Copending application, Ser. No. 758,365, entitled, "Programmable
Frequency Converting Filter," by Lawrence Reagan, filed Jan. 5, 1977,
assigned to the same assignee of this application, describes how the
passbands of a charge transfer device transversal filter are programmed in
response to a clocking frequency.
In one preferred embodiment, the parameters N.sub.0 and N.sub.1 are chosen
such that the passbands of filter 700 have a center frequency of N .times.
f.sub.s2 .times.1/4f.sub.s2, and the bandwidth of filter 700 equals
1/20f.sub.s2. FIG. 3f illustrates the frequency response of the charge
coupled device filter having the above described characteristics. The
function of the filter 700 is to receive signals S7 on lead 701, to filter
a selected one of the channels (either AM or sideband) from the plurality
of channels comprising signal S7, and to frequency shift the selected
channel down in frequency.
If the selected channel is a single sideband channel, the channel has a
width of approximately 5 kHz and thus filter 700 is clocked with a
frequency f.sub.s2 such that its passbands are approximately 5 kHz wide.
In other words, the quantity 1/20 f.sub.s2 approximately equals 5 kHz when
the selected channel is a single sideband channel. Additionally, the
frequency f.sub.s2 is chosen such that one of the multiple passbands of
filter 700 aligns with the sideband channel to be selected from S7. In the
preferred embodiment, the passband of filter 700 that is centered at
5f.sub.s2 + 1/4f.sub.s2 is aligned with the sideband channel selected from
signal S7. This is filter 700' s eleventh passband. As illustrated in
Table IIIa, a frequency f.sub.s2 equal to 86,409 Hz aligns the center of
the eleventh passband of filter 700 with frequency 450 kHz. And a clocking
frequency f.sub.s2 of 86,932 Hz aligns the center of the eleventh passband
of filter 700 at 460 kHz. The width of both of these passbands is
approximately 5 kHz. FIG. 3E1 is a blow up of signal S7 about the
frequency of 455 kHz, and FIG. 3F1 is a blow up of FIG. 3F about the same
frequency. Together, these figures illustrate the alignment of the
eleventh passband of filters 700 with the selected channel. It should also
be noted, as illustrated in FIG. 3E1, that the mixing operation of mixer
300 results in the flip-flopping in frequency of the upper and lower
sideband channels. This flip-flopping occurs because the mixing frequency
of 3.58mHz is higher than the center frequency of the selected AM channel,
i.e., 3.125mHz.
The clocking frequency f.sub.s2 is also chosen such that filter 700 has
bandwidths of approximately 10 kHz, one of which is centered about the
frequency of 455 kHz. Such a characteristic is used to pass an AM signal
centered about 455 kHz. Table IIIb illustrates that a clocking frequency
f.sub.s2 equal to 202,218 Hz causes filter 700 to have its passband
centered at 455 kHz and a bandwidth of approximately 10 kHz. This
situation is also illustrated in FIGS. 3E1 and 3F1.
TABLE IIIa
______________________________________
##STR1##
##STR2## f.sub.s2
______________________________________
5 kHz 450 kHz 86,409 Hz
5 kHz 460 kHz 86,932 Hz
______________________________________
TABLE IIIb
______________________________________
##STR3##
##STR4## f.sub.s2
______________________________________
10 kHz 455 kHz 202,218 Hz
______________________________________
Lead 703 couples the output of CCD filter 700 to an amplifier 800.
Amplifier 800 is tuned to pass only those frequencies lying within the
first passband of CCD filter 700. That is, amplifier 800 only passes
frequencies lying about 1/4 f.sub.s2. Amplifier 800 has an output lead 801
and signals S9 are generated thereon. FIG. 3G illustrates signal S9 on the
same frequency scale as FIG. 3F (which illustrates the passbands of filter
700); and FIG. 3H illustrates signal S9 on an expanded frequency scale so
that its characteristics are more apparent. In FIG. 3H, the signal S9 is
illustrated as lower sideband channel L2 as an example.
Signal S9 is coupled to a demodulator 900 via the lead 801. Demodulator 900
functions to shift signals S9 in frequency to the audio range. When
sideband signals are received, this shift in frequency is accomplished by
time sampling signal S9 at a third selectable f.sub.s3. Time sampling
equals convolution in the frequency domain. FIG. 3I illustrates the
frequency components of a sampling transfer function H2 which samples at a
frequency f.sub.s3 and FIG. 3J illustrates the convolution of signal S9
with transfer function H2. This convolution signal is labeled S10 and is
generated on a lead 901.
In order to properly shift signal S9 to the audio frequency range by the
convolution operation, it is necessary that the frequency f.sub.s3 be
carefully aligned frequencies of S9. When signal S9 is a lower sideband,
frequency f.sub.s3 is chosen to align with the lowest frequency present.
Thus, in FIG. 3H, frequency f.sub.s3 lies to the left of the quantity
f.sub.s2 /4, and nominally is 20.346 kHz.
One difficulty in receiving single sideband signals is that they have no
carrier to lock onto. Thus, the exact position in frequency of the signal
S9 is unknown. All that is known is that the signal lies somewhere within
its assigned 5kHz channel; and therefore a problem exists in being able to
align frequency f.sub.s3 with signal S9 regardless of where the latter
lies within its channel. The tone quality of the resulting audible signal
is directly related to how well frequency f.sub.s3 and signal S9 are
aligned. Elements 3200-3500 provide a means for incrementally adjusting
frequency f.sub.s3 so as to be properly aligned with signal S9 regardless
of where it lies within its 5-kHz channel.
As described above, amplitude modulated signals may also be received. In
that case, frequency f.sub.s2 equals 202,218; and therefore signal S9
which is centered at f.sub.s2 /4 has a center frequency of 50.555 kHz.
Demodulator 900 shifts this signal to the audio range by a standard diode
envelope detector which does not require a third sampling frequency.
Signal S10 couples via lead 901 to volume control unit 1000. Volume control
unit 1000 has an output lead 1001 and signals S11 are generated thereon.
Lead 1001 couples to an audio amplifier 1100 which has an output lead 1101
and signals S12 are generated thereon. Lead 1101 is coupled to a speaker
30 where the signals S12 shown in FIG. 3 are converted to audible sound.
As previously described, switch 600 has signal inputs coupled to leads 501
and 502, and an output coupled to lead 701. A logic signal determines
whether lead 501 or 502 is coupled to lead 701 dependent upon whether the
transceiver is in a receive mode or a transmit mode, respectively.
FIG. 4 is a greatly enlarged top view of CCD transversal filter 700. Lead
701 couples to an input stage 710 of filter 700. Lead 702, carrying
clocking signals of the second selectable frequency f.sub.s2, couples to
the clocking input 711 of filter 700. As previously described, filter 700
is comprised of a plurality of serially-connected stages 712; and each of
the stages has a split electrode. These splits 713 have a profile of the
form (sine N/N) (cosine 2.pi.f.sub.0 N). This structure has a plurality of
passbands centered about multiples of the frequency f.sub.s2 as previously
described. Lead 703 couples to an output stage 714 of filter 700, and the
signals S8 are generated thereon.
As the preceding description indicates, the operation of the transceiver of
FIG. 2 is dependent upon the proper generation of three selectable
frequencies f.sub.s1, f.sub.s2, and f.sub.s3. The clocking means for
generating these frequencies will now be described. FIG. 2 illustrates
these clocking means in block diagram form. They are comprised of clocking
modules 3000, 3100, and 3200. Basically, module 3000 generates signal S301
which is comprised of a fixed frequency of 3.58 mHz. Module 3000 also
generates signals S3004 and S3005 on leads 3004 and 3005, respectively.
Lead 3004 couples to module 3100, which in response to S3004 generates
signals S202 comprised of frequency f.sub.s1. Lead 3005 couples to module
3200 which receives signals S3005 and, in response thereto, generates
signals S702 and S902 comprised of frequencies f.sub.s2 and f.sub.s3,
respectively.
The selectable frequencies f.sub.s1, f.sub.s2, f.sub.s3 are generated by
modules 3000 and 3200 as multiples of 3.58 mHz. These multiples are
designated as N.sub.1 -N.sub.6 in FIG. 2. Some of the multiples are fixed,
while other multiples are programmable. TABLE IV lists the selectable
frequencies, f.sub.s1, f.sub.s2, f.sub.s3 along with the multiples N.sub.1
-N.sub.6 and the intermediate clocking signals S3004 and S3005 as a
function of the particular single sideband channel or AM channel that is
to be received.
TABLE IV
__________________________________________________________________________
SSB-CH AM-CH
1L 1U 2L 2U 1 2
__________________________________________________________________________
osc 3.58MHZ
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
f.sub.s1
23.84MHZ
23.84MHZ
23.85MHZ
23.85MHZ
23.84MHZ
23.85MHZ
N.sub.2
1432 .fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
S3004
2.5KHZ
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
N.sub.1
9,536 .fwdarw.
9,540 .fwdarw.
9,536 9,540
f.sub.s2
86,932HZ
86,409HZ
86,932HZ
86,409HZ
202,218HZ
N.sub.3
10 .fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
S3005
250HZ .fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
.fwdarw.
N.sub.4
55 .fwdarw.
.fwdarw.
.fwdarw.
24 .fwdarw.
.fwdarw.
N.sub.5
19,125
19,010
19,125
19,010
19,413
19,413
f.sub.s3
20,345HZ
22,959HZ
20,345HZ
22,959HZ
H H
N.sub.6
235 207 235 207 X X
__________________________________________________________________________
Some of the information in TABLE Iv can be correlated with the preceding
description. Compare, for example, the f.sub.s1 frequency listings of
TABLE II, with the entries in TABLE IV. Also compare the TABLE III entries
of f.sub.s2, with the TABLE IV entries of f.sub.s2. And further compare
the demodulating clocking frequency f.sub.s3 of FIGS. 3I and 3I1 with the
f.sub.s3 entries in TABLE IV.
Given the values of f.sub.s1, f.sub.s2 and f.sub.s3 as listed in TABL IV,
N.sub.1 -N.sub.6 must be chosen such that the desired frequencies are
obtained. To this end, multiplier N.sub.2 is chosen to be 1432. Thus,
signal S3004 is a fixed frequency of 2.4 kHz. Accordingly, a selectable
frequency f.sub.s1 of 23.84 kHz is obtained by setting N.sub.1 to 9,536 or
9,540, respectively.
As TABLE IV further illustrates, the multiplier N.sub.3 is fixed at a value
of 10. Thus, signal S3005 is a fixed frequency of 250 Hz. And therefore,
selectable frequency f.sub.s2 becomes 86,932 (as required to receive lower
sideband signals) when multipler N.sub.5 equals 19,125. Similarly,
frequency f.sub.s2 equals 86,409 or 202,218 when multiplier N.sub.5 equals
19,010 or 19,413, respectively.
Selectable frequency f.sub.s3 is generated by appropriately choosing
N.sub.6. As illustrated in TABLE IV, frequency f.sub.s3 is suitable for
demodulating lower sideband channels when N.sub.6 equals 235, and is
suitable for demodulating upper sideband channels when multiplier N.sub.6
equals 207.
As the preceding description pointed out, sideband signals may lie anywhere
within their assigned 5-kHz channel, and thus it is desirable to control
the selectable frequency f.sub.s2 in fine increments. TABLE IV implies how
this fine incremental control is obtained. Signal S3005 has a fixed
frequency of 250 hertz and multiplier N.sub.4 is fixed at 55. This
produces a frequency of 250 Hz/55 or approximately 5 Hz. Thus, by
constructing multiplier N.sub.5 as a programmable multiplier, frequency
f.sub.s2 is controllable in increments of approximately 5 Hz.
Referring to FIG. 5, the details of clocking module 3000 are therein
illustrated. Clocking module 3000 is comprised of a 3.58 mHz oscillator
3,020, a divide by N.sub.2 logic circuit 3040 and divide by 10 logic
circuit 3060. This configuration is illustrated in block diagram form in
FIG. 5a.
As illustrated in FIG. 6A, clocking module 3100 is implemented by means of
a phase lock loop. The phase lock loop is comprised of a phase detector
3120, a voltge controlled oscillator (VCO) 3140, and a programmable
counter 3160. Phase detector 3120 has a first input coupled to lead 3004
and a second input coupled to an output of programmable counter 3160 via a
lead 3161. A lead 3121 couples an output of phase detector 3120 to an
input of VCO 3140. Lead 202 couples an output of VCO 3140 to an input of
counter 3160 thereby completing the phase locked loop. Phase detector 3120
is illustrated in detail in FIG. 6B. It includes a logic gate 3122 having
an input coupled to lead 3004 and an output coupled to an RC ramp
generating circuit 3123. An operational amplifier 3124 is provided to
buffer the output of the ramp generating circuit 3123. A
logically-controlled switch 3125 has a signal input which couples to an
output of operational amplifier 3124, and a logical control input which
couples to a lead 3161. An output of switch 3125 couples to a holding
capacitor 3126, and to the input of an operational amplifier 3127. Lead
3121 couples to an output of operational amplifier 3127. In this
configuration, signal S3004 causes a ramp signal to be generated at the
output of operational amplifier 3124, and switch 3125 samples the ramp
signal in response to signal S3161. The sample is stored in holding
capacitor 3126 and buffered by operational amplifier 3127. Thus, signal
S3121 has a magnitude which reflects the phase difference between signals
S3004 and S3161.
FIG. 6C is a detailed circuit diagram of VCO 3140. As therein illustrated,
the VCO is comprised basically of a dual gate MOS-FET 3141 having one gate
coupled to a biasing network 3142, and having a second gate coupled to a
tuned circuit 3143. The tuned circuit includes a vari-cap 3144 which has a
capacitance proportional to the voltage applied across its terminals.
Thus, the resonant frequency of the circuit 3143 is dependent upon the
voltage applied across vari-cap 3144. Signal S3121 is coupled to the
vari-cap, and therefore, the oscillating frequency of circuit 3143 is
responsive to the magnitude of that signal. The source of FET 3141 is
coupled to a buffering transistor 3145. Lead 202 couples to the collector
of transistor 3145, and signals S202, having the first selectable
frequency, are generated thereon.
Counter 3160 is comprised of a fixed divide-by-four counter 3162, and
programmable 12-bit counter 3163. Lead 202 couples to the input of
divide-by-four counter, and a lead 3164 couples the divide-by-four counter
output to the programmable 12-bit counter input. FIG. 6D is a detailed
logic diagram of the 12-bit counter 3163. It is basically constructed of
three 4-bit counters 3165-3167. Each of these counters is identical in
construction to the previously-described counters 3044 and 3045. Counters
3165-3167 are serially coupled together to form one 12-bit counter.
Programmable logic signals A0-A5 are supplied to the least significant six
inputs of counter 3163 via lead 3401. Inputs to the most significant six
bits of counter 3163 are fixed at either a 1 or a 0 logic level. Utilizing
this configuration, counter 3163 has a programmable count defined in
binary as 100100XXXXXX. The complement of this count is loaded into
counter 3163 when its carryout is true. Logic gates 3168 are coupled to
provide the necessary control signals on the LD inputs of counters
3165-3167.
FIG. 6E is a detailed circuit diagram, of an alternative embodiment of
phase detector 3120. The phase detector has a reference clock input lead
3004, a sampling clock input lead 3161, and a phase detection | | |
