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Linearizing network
   
Document Number
US Patent 4140981
Issued Date
February 20, 1979
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Abstract
A linearizing circuit is described which gives a nonlinear relation between an input and an output signal of the circuit. Such a circuit can be used to compensate for the nonlinearity in, for example, a frequency modulator. The circuit includes a nonlinear element, preferably a PIN-diode connected in a voltage divider to provide a biasing current to the element. An attenuating and an amplifying circuit are connected to the input and to the output, respectively, of the circuit. By varying the values of the attenuation/amplification and the value of the operation point of the element, the nonlinearity of the circuit can be varied.
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Linearizing network - US Patent 4140981 Drawing
Drawing from US Patent 4140981
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Number of Claims:
4
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Owner
Published
February 20, 1979
Application Number
05/879,736
Filed
February 21, 1978
US Classification
332/124   327/317 327/334 331/177V 702/86
Int'l Classification
H03C   3/08   (20060101)   H03C   3/00   (20060101)  
Examiner
Priority Data
Mar 03, 1977 [SE] 7702344
USPTO Field of Search
332/18   332/3V   331/36C   331/177V   328/142   328/184   307/229   307/230  
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