Recorder memory with variable read and write rates

What is claimed is:

1. A memory and memory control apparatus therefor adapted to write pulse coded data into addressable locations at one rate and to read pulse coded data from other addressable locations at another rate, the write and read operations being performed substantially independently of each other, comprising:

a memory having plural addressable locations whereat pulse coded data are stored, respectively;

write address generating means for generating selected addresses corresponding to said addressable locations of said memory;

read address generating means for generating selected addresses corresponding to said addressable locations of said memory;

means for supplying pulse coded data;

clock pulse generating means for generating write clock pulse signals at a first rate and read clock pulse signals at a second rate different from said first rate;

write-in means for writing said pulse coded data into said memory at locations therein determined by said write address generating means during write intervals determined by said write clock pulse signals;

read-out means for reading pulse coded data out of said memory from locations therein determined by said read address generating means at read intervals determined by said read clock pulse signals; and

means for selectively enabling a write-in and read-out operation during said write and read intervals, respectively, depending upon the time of occurrence of said write and read clock pulse signals with respect to each other.

2. The apparatus of claim 1 wherein said selectively enabling means comprises means responsive to each write clock pulse signal to define a timing interval comprised of a predetermined first portion and a second portion; first gating means responsive to said first portion of said timing interval for actuating said write-in means to write said pulse coded data into said memory; and second gating means enabled by said second portion of said timing interval and responsive to each read clock pulse signal for actuating said read-out means to read said pulse coded data out of said memory and to inhibit said first gating means for a preselected time duration.

3. The apparatus of claim 2 wherein said first gating means includes write pulse generating means for generating a write gate pulse of pre-established duration to actuate said write-in means; and wherein said second gating means includes read gate pulse generating means being energized to generate a read gate pulse of said preselected time duration in response to the occurrence of said read clock pulse signal during said second portion of said timing interval and being further energized by the termination of said write gate pulse.

4. The apparatus of claim 3 further comprising means for supplying said first gating means with said read gate pulse to inhibit said write gate pulse generating means from generaing said write gate pulse when said read gate pulse is present.

5. The apparatus of claim 4 wherein each of said write and read gate pulse generating means is comprised of monostable multivibrator means triggered to an unstable condition for generating a respective write and read gate pulse.

6. The apparatus of claim 3 wherein each of said write and read address generating means comprises counting means responsive to a respective write and read clock pulse signal for incrementing the count thereof; and further comprising selecting means coupled to the write and read counting means and selectively responsive to said read gate pulse for producing either the count supplied by said write counting means or the count supplied by said read counting means.

7. The apparatus of claim 6 wherein said write and read address generating means further comprises decoding means coupled to said selecting means and responsive to the count selectively produced thereby to determine a corresponding location in said memory.

8. The apparatus of claim 7 wherein said means for supplying pulse coded data supplies serial bits of data; said write clock pulse signals are generated at the serial bit supply rate; and said decoding means determines each of the data bit locations in said memory.

9. The apparatus of claim 1 wherein said write address generating means comprises write address counting means for counting each of said write clock pulse signals; said read address generating means comprises read address counting means for counting each of said read clock pulse signals; and further comprising selecting means having one set of inputs coupled to said write address counting means, another set of inputs coupled to said read address counting means; a control input coupled to said selectively enabling means, and outputs to which the counts of said write and read address counting means are selectively applied depending upon whether a write-in or a read-out operation is enabled.

10. The apparatus of claim 9 wherein said means for supplying pulse coded data comprises means for supplying pulse coded data serially by bit; and timing means supplied with said serial data bits with said write clock pulse signals for synchronizing said serial data bits to the write clock pulse signal repetition rate.

11. Apparatus for using a video recorder to record pulse encoded data representing audio information having simulated horizontal and vertical synchronizing signals therein, said apparatus being operable on said pulse encoded data and comprising:

a memory having plural addressable locations whereat pulse coded data is stored; and

memory control means for controlling the writing of pulse coded data into and the reading out of pulse coded data from said memory, comprising:

clock pulse generating means for generating write clock pulse signals at a first rate and read clock pulse signals at a second rate different from said first rate;

write address generating means responsive to said write clock pulse signals for generating selected addresses of said memory locations intho which pulse coded data is to be written;

read address generating means responsive to said read clock pulse signals for generating selected addresses of said memory location from which pulse coded data is to be read;

write-in means for writing said pulse coded data into said memory at said addresses generated by said write address generating means during write intervals determined by said write clock pulse signals;

read-out means for reading pulse coded data out of said memory from addresses generated by said read address generating means during read intervals determined by said read clock pulses; and

means for delaying the relative operation of one of said write-in and read-out means in the event that the other is operating.

12. The apparatus of claim 11 wherein said write address generating means comprises a write address counter for counting said write clock pulse signals; said read address generating means comprises a read address counter for counting said read clock pulse signals; and further comprising selecting means coupled to both said write and read address counters for selectively producing either the count of said write address counter or the count of said read address counter as the location address for said memory.

13. The apparatus of claim 12 wherein said delaying means comprises means responsive to each write clock pulse signal for defining a predetermined write-enable time duration and a read-enable time duration; write gate pulse generating means for generating a write gate pulse during said write-enable time duration; read gate pulse generating means for generating a read gate pulse during each read-enable time duration in response to each read clock pulse signal; first inhibit means coupled to said write gate pulse generating means for inhibiting said write gate pulse while said read gate pulse is generated; and second inhibit means coupled to said read gate pulse generating means for inhibiting said read gate pulse during said write-enable time duration.

14. The apparatus of claim 13 wherein said read gate pulse generating means further comprises means for sensing the termination of said write gate pulse; and means responsive either to said read clock pulse signal generated during said read-enable time duration or to said termination of said write gate pulse for generating said read gate pulse.

15. The apparatus of claim 14 further comprising means for supplying said read gate pulse to said selecting means to cause said selecting means to produce said count of said read address counter as said location address for said memory.

16. The apparatus of claim 15 wherein said read gate pulse generating means includes means for generating the complement of said read gate pulse; and further comprising means for supplying said read gate pulse complement to said selecting means to cause said selecting means to produce said counter of said write address counter as said location address for said memory.

17. The apparatus of claim 16 wherein said means for defining said write-enable and said read-enable time duration comprises first monostable multivibrator means.

18. The apparatus of claim 17 wherein said write gate pulse generating means comprises second monostable multivibrator means triggered by said first monostable multivibrator means; and said first inhibit means comprises first gate means disabled by said read gate pulse to prevent said second monostable multivibrator means from being triggered.

19. The apparatus of claim 18 wherein said read gate pulse generating means comprises third monostable multivibrator means triggered by said read clock pulse signals or to the termination of such write gate pulse; and said second inhibit means comprises second gate means disabled by said first monostable multivibrator means to prevent said third monostable multivibrator means from being triggered by said read clock pulses.

20. The apparatus of claim 16 wherein said write-in means comprises timing means for receiving said pulse coded data and responsive to said write clock pulse signals for synchronizing said pulse coded data to said first rate; and write-in gates for receiving said synchronized pulse coded data and responsive to said write gate pulse to write said synchronized pulse coded data into said memory.

21. The apparatus of claim 20 wherein said read-out means includes gating means responsive to said read gate pulse; and retiming means for receiving the output of said last-mentioned gating means and responsive to said read clock pulse signals for synchronizing said pulse coded data to said second rate.

22. The apparatus of claim 21 further including means for reproducing said pulse coded data and said simulated horizontal and vertical synchronizing signals from said magnetic medium; means for supplying said reproduced pulse coded data to said timing means included in said write-in means; converter means for converting said pulse coded data to analog form; and means for supplying the pulse coded data synchronized to said second rate by said retiming means to said converter means.

23. The apparatus of claim 22, further comprising means for selectively establishing a recording or reproducing mode of operation; and wherein said clock pulse generating means generates write clock pulse signals at a slower rate than said read clock pulse signals during a recording operation and at a faster rate than said read clock pulse signals during a reproducing operation.

24. The apparatus of claim 22 wherein said pulse coded data is written into and read out from said memory serially by bit; and wherein each addressable memory location stores a single data bit.

25. A method of controlling an addressable memory to change the repetition rate of pulse coded data bits supplied thereto, comprising the steps of:

generating write clock pulses having a repetition rate equal to the repetition rate at which said pulse coded data bits are supplied;

generating read clock pulses having a different repetition rate;

generating bit write addresses in synchronism with the repetition rate of said write clock pulses;

generating bit read addresses in synchronism with the repetition rate of said read clock pulses;

establishing a write cycle during the interval between successive write clock pulses to write said supplied data bit into the memory at the generated bit write address;

establishing read cycle during the interval between successive read clock pulses to read a data bit out of said memory from the generated bit read address; and

delaying the relative occurrences of one of said read and write cycles in the event that the other cycle is being performed.

26. The method of claim 25 wherein said step of establishing a write cycle comprises generating a write-in gate pulse in response to a write clock pulse; and gating a data bit into said memory during the duration of said write-in gate pulse.

27. The method of claim 26 wherein said step of establishing a read cycle comprises generating a read-out gate pulse in response to a read clock pulse; applying the generated bit read address to said memory during the duration of said read-out gate pulse to read a data bit out of said memory; and transmitting said read-out data bit in response to said read-out gate pulse.

28. The method of claim 27 wherein said step of delaying comprises generating a periodic pulse of predetermined duration in response to each write clock pulse; inhibiting said read-out gate pulse from being generated during said periodic pulse duration; and inhibiting said write-in gate pulse from being generated during the duration of said read-out gate pulse.

29. The method of claim 28 wherein said write-in gate pulse is generated when said periodic pulse is generated and said read-out gate pulse is not generated.

30. The method of claim 28 comprising the further step of also generating said read-out gate pulse at the conclusion of said write-in gate pulse and extending the duration of said read-out gate pulse in response to the next read clock pulse.

31. The method of claim 30 comprising the further step of synchronizing the transmitted data bits read out of said memory with said read clock pulses.

32. The method of claim 28 comprising the further steps of generating a complementary read-out gate pulse; and applying the generated bit write addresss to said memory during the duration of said complementary read-out gate pulse.

33. The method of claim 25 wherein said read clock pulses are generated at a faster rate than said write clock pulses to time-compress the repetition rate of said supplied pulse coded data bits.

34. The method of claim 25 wherein said write clock pulses are generated at a faster rate than said read clock pulses to time-expand the repetition rate of said supplied pulse coded data bits.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

This invention relates to a pulse storage memory and, more particularly, to an addressable memory and a method of and apparatus for controlling that memory. This invention further relates to a particular use of an addressable memory for the purpose of changing the repetition rate of pulse data when such data is recorded on or reproduced from a magnetic medium.

A magnetic video recorder, such as a video tape recorder (VTR) exhibits a sufficiently wide recording bandwidth such that it can be used to record audio signals with extremely high fidelity. A conventional type of VTR, when used to record an NTSC color video signal, records such a signal in parallel slant tracks, each track having a video field recorded therein. In view of the relatively low frequencies of an audio signal, there is a far greater signal storage capacity in each slant track than is needed for the audio signal. Accordingly, it is not advantageous to record an analog audio signal in place of a video signal in the slant tracks of a VTR.

If an audio signal is encoded into a digital signal, such as a PCM data signal, the resultant pulse signals can be processed without a concomittent loss in signal information. That is, the pulse signals can be transmitted or recorded with great accuracy. However, in order to exhibit the necessary high bandwidth for magnetically recording such a pulse signal, suitable magnetic recording equipment heretofore has been very expensive. A VTR of the type now available for home video recording use is far less expensive than professional-type high bandwidth magnetic recording equipment, yet such a VTR offers a satisfactory bandwidth characteristic to permit the magnetic recording of a pulse encoded audio signal.

The recording head or heads of a VTR of the aforementioned type generally is capable of recording a single channel, such as a serial pulse train. Hence, when an audio signal is encoded into pulse form, it is convenient to serialize such a pulse encoded data signal. During recording, the serialized pulse train produced by the pulse encoding device, such as an analog-to-digital converter, need not be of the same repetition rate as the pulse recording frequency. In one example, the pulse recording frequency is a function of the VTR parameters and, therefore, is related to the television synchronizing frequencies, such as the horizontal synchronizing frequency, of the video signal which normally is recorded on the VTR. In such an example, the pulse recording frequency is higher than the serialized encoded pulse repetition rate. Similarly, when a recorded pulse signal is played back from a VTR and is reconverted into an analog audio signal, the pulse reproduction rate generally is greater than the serialized pulse repetition rate which is supplied to a digital-to-analog converter. Hence, to accommodate these different pulse rates, apparatus is needed to compress the time domain of the pulse signals during recording and to expand the time domain of the pulse signals during reproduction.

One technique which heretofore has been used for time compression or expansion has required a plurality of memory devices. Pulses of a first repetition rate are serially written into a first memory by using a write clock pulse signal whose frequency is equal to the input pulse rate. When this first memory has been filled, the stored pulses are transferred to a second memory device at, for example, a read clock pulse rate which differs from the write clock pulse rate, and subsequently the pulse signals stored in the second memory device are read out to the magnetic recording transducers. If this technique is used in combination with a VTR, the capacity of each of the memory devices must be large enough to accommodate all of the pulse signals which are to be recorded in a slant track. This is necessary to avoid any interference between the incoming pulse signals, such as those produced by the analog-to-digital converter, and the outgoing pulse signals, such as those supplied to the VTR, while accommodating the desired compression or expansion of the time domain. In view of this very high memory storage capacity needed by the aforementioned technique, the cost of such memory devices is extremely high. Hence, this technique generally is economically useful only for the time-compression or -expansion of a small number of data pulses.

Another technique for changing the time domain of a pulse signal relies upon a shift register of the so-called "first-in, first-out" type wherein write and read operations can be performed on the shift register simultaneously. However, such a shift register is quite expensive such that its cost per bit renders it economically undesirable. Also, the control circuitry which must be used with such a shift register adds to the overall cost in carrying out this technique.

OBJECTS OF THE INVENTION

Therefore, it is an object of the present invention to provide improved apparatus and a method of using same for varying the time domain of a pulse signal, whereby the aforenoted disadvantages are avoided.

Another object of this invention is to provide an improved memory circuit and memory control apparatus which is useful in compressing or expanding the time domain of a pulse signal applied thereto.

A memory circuit which is useful for this application is an addressable memory, such as a random access memory (RAM). In a RAM, pulse signals may be written into addressed locations at a write clock pulse rate and stored pulse signals may be read from different addressed locations at a read clock pulse rate, the write and read clock pulse rates being different from each other. Hence, if the read clock pulse rate exceeds the write clock pulse rate, time compression is achieved. Conversely, if the write clock pulse rate exceeds the read clock pulse rate, then time expansion is achieved,

Therefore, a further object of this invention is to provide an addressable memory and a method of and apparatus for controlling that memory for the purpose of varying the time domain of pulse signals applied thereto.

When using a RAM, write and read operations generally can be interleaved. Hence, during a given time duration during which may write and read cycles are performed, it would appear that the write and read operations are carried out substantially simultaneously. However, since the write operation is performed at one rate and the read operation is performed at another rate, it is possible that some instant will be reached when a write and read operation occur simultaneously in time.

Therefore, it is yet another object of this invention to provide a method of and apparatus for controlling an addressable memory for writing in and reading out data therefrom whereby write and read operations can be performed during successive write and read intervals, but the simultaneous occurrence of such operations is prevented.

An additional object of this invention is to provide a method of and apparatus for controlling an addressable memory into which pulse data is written during a write cycle which can occur during periodic write intervals and from which data is read during a read cycle which can occur during periodic read intervals, the relative occurrence of a write cycle or a read cycle being delayed in the event that the other is present.

A still further object of this invention is to provide an improved method of and apparatus for controlling a relatively inexpensive, low capacity addressable memory for the purpose of changing the time domain of a pulse signal which is recorded on or reproduced from a slant track on a magnetic medium by a magnetic video recording device.

Various other objects, advantages and features of the present invention will become readily apparent from the ensuing detailed description, and the novel features will be particularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

In accordance with the present invention, an addressable memory is provided together with apparatus for controlling that memory such that pulse data at a first rate is written into selected ones of the memory addresses and pulse data at a second rate is read out from different memory addresses. A clock pulse generator generates periodic write clock pulses at a write clock rate and read clock pulses at a periodic read clock rate. The write clock pulses are used to generate successive memory addresses into which pulse data is to be written; and the read clock pulses are used to generate successive memory addresses from which stored pulse data is to be read. A write-in circuit generates a write-in cycle during the interval between successive write clock pulses; and a read-out circuit generates a read out cycle during the interval between successive read clock pulses. A control circuit detects whether a write-in and read-out cycle will coincide, and is operable to selectively delay one or the other of the write-in and read-out cycles during its respective interval.

The present invention also relates to a method of controlling an addressable memory such that pulse data can be written into addressed memory locations substantially independently of the reading out of pulse data, that is, either a write-in or read-out operation can be performed irrespective of the particular operation that had been performed previously.

In accordance with another feature of this invention, an addressable memory and memory control circuit are used in combination to achieve compression or expansion of the time domain of input pulse data. A useful application of this feature is to record and reproduce pulse data on a conventional type magnetic video recorder.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example, will best be understood in conjunction with the accompanying drawings, wherein:

FIG. 1 is an overall system block diagram wherein the present invention finds ready application;

FIGS. 2A-2C are waveform diagrams representing how the system of FIG. 1 operates;

FIG. 3 is a block diagram showing a portion of the system of FIG. 1 in greater detail;

FIGS. 4A and 4B are block diagrams of the memory and memory control apparatus shown in FIG. 3;

FIGS. 5A-5J are waveform diagrams which are useful in explaining the operation of the memory and memory control apparatus during a signal recording operation, for example;

FIGS. 6A-6J are waveform diagrams which are useful in explaining the operation of the memory and memory control apparatus during a signal reproducing operation;

FIG. 7 is a logic circuit diagram of one of the control circuit blocks shown in FIG. 4;

FIGS. 8A-8O are waveform diagrams which are useful in explaining the operation of the circuit shown in FIG. 7 during a signal recording operation, for example; and

FIGS. 9A-90 are waveform diagrams which are useful in explaining the operation of the circuit shown in FIG. 7 during a signal reproducing operation.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Overall System

Referring now to the drawings, and in particular to FIG. 1, there is illustrated a block diagram of one embodiment of apparatus which can be used to record signals, and particularly pulse signals, onto a magnetic video recorder, such as a video tape recorder (VTR) 1, and to produce such signals therefrom. As is known, VTR 1 is adapted for normal operation to record and play back video signals. For this purpose, VTR 1 includes circuitry that utilizes the synchronizing signals normally accompanying a video signal to particularly control a recording and a playback operation. As one example, VTR 1 is of the type having two rotary heads spaced 180.degree. apart that scan successive slant tracks across magnetic tape, each such track having one field of an NTSC signal recorded therein. Such a VTR has a bandwidth that is sufficiently wide so as to be capable of recording pulse signals in the slant tracks. Since, in the conventional VTR, each rotary head records and reproduces a serial signal, these heads can be used to record and reproduce pulse signals in serial form. While these pulse signals can, of course, represent a wide variety of data, or information, the system shown in FIG. 1 will be described for the application wherein analog audio signals are represented by pulse signals. This can be achieved by sampling audio signals, for example, left and right stereo signals, and suitably encoding each sample, as by pulse code modulation (PCM) encoding.

In order to understand better the following description and appreciate the improvements achieved by the system of FIG. 1, an explanation of preferred parameters now is given. Practically, VTR 1 is capable of recording 1,400,000 bits per second (1.4M bit/sec.), thus having a pulse signal recording rate corresponding to 1.4 MHz. If the audio signal is to be enabled to undergo a dynamic range of 90dB for high fidelity recording, a sampled signal should be encoded with 13 bits. Hence, if left and right stereo signals are contemplated, then each digital word is comprised of 26 bits (13 bits per channel). Now, in a conventional VTR, it is convenient for the frequency of the signal that is recorded to be related to the horizontal synchronizing signal frequency f.sub.h so that the recording signal frequency f.sub.t =nf.sub.h, where n is an integer, but f.sub.t < 1.4 .times. 10.sup.6 /26 or f.sub.t should be less than 53.85 KHz. Also, each slant track has one field of a video signal recorded therein, and each field is comprised of 262.5 horizontal line intervals. However, useful information, that is, pulse encoded audio information, is not recorded during the vertical synchronizing interval which, generally, is comprised of about twenty horizontal line intervals (20H).

If it is assumed that the maximum frequency in the audio signal to be recorded is approximately 20 KHz, then the minimum sampling frequency f.sub.s necessary to encode this audio signal is twice the maximum frequency, or 40 KHz. Therefore, the minimum recording signal frequency should be greater than the ratio between the number of horizontal line intervals in a field and the number of useful horizontal line intervals in that field, times the minimum sampling frequency, that is, f.sub.t > (262.5/262.5-20) .times. 40.times.10.sup.3 or f.sub.t > 43.3 KHz. The following summary of the foregoing conditions 43.3 KHz < (f.sub.t =nf.sub.h) < 53.85 KHz is satisfied by:

f.sub.t = 3f.sub.h = 3.times. 15.75 KHz = 47.25 KHz.

Consistent with this expression, the sampling frequency f.sub.s may be expressed as f.sub.s = (262.5-20/262.5) .times. f.sub.t = 43.65 KHz. However, the sampling frequency f.sub.s should be related to the recording signal frequency f.sub.t by an integral number. If f.sub.t /f.sub.s = 15/14, as an example, then f.sub.s = 44.1 KHz. Thus, the number of samples N recorded in each field is equal to the sampling frequency f.sub.s divided by the duration of a field, N = 44.1 .times. 10.sup.3 /60 = 735. As mentioned above, each sample is formed of a 26-bit word with 13 bits representing the left-channel audio signal and 13 bits representing the right-channel, audio signal of a stereo signal. Also, three words (or three left and right channel samples) are provided during each horizontal line interval. Hence, the number of horizontal line intervals during each field that are occupied by pulse encoded audio signals is equal to 735/3, or 245 lines intervals. Thus, the vertical blanking interval in each field should be 262.5-245 =17.5H, or 17.5 horizontal line intervals.

The apparatus of FIG. 1 operates with the foregoing parameters to record pulse encoded audio signals on a magnetic medium and to reproduce such signals therefrom. As shown, the system includes a recording channel comprised of a low-pass filter 4L, a sampling circuit 5L, an analog-to-digital (A/D) converter 6L and a parallel-to-serial converter 7 for the left channel and a low-pass filter 4R, a sampling circuit 5R, an analog-to-digital (A/D) converter 6R and parallel-to-serial converter 7 for the right channel. The system also includes a reproducing channel comprised of a serial-to-parallel converter 17, digital-to-analog (D/A) converter 18L and low-pass filter 19L for the left channel and serial-to-parallel converter 17, a digital-to-analog (D/A) converter 18R and a low-pass filter 19R for the right channel. As may be appreciated, the recording channel is adapted to supply the pulse encoded audio signals (hereinafter, pulse signals) to VTR 1 for recording, while the reproducing channel is adapted to supply the pulse signals reproduced by VTR 1 to suitable sound reproduction devices (not shown). To accommodate the different sampling and recording frequencies f.sub.s and f.sub.t, respectively, a memory device 8 is provided between the recording channel and the VTR, while a memory device 16 is provided between the VTR and the reproducing channel. In a practical embodiment, both memory devices are combined into a single addressable memory, such as a random access memory (RAM) that is used selectively during a recording or reproducing operation.

Low-pass filter 4L is coupled to an audio input terminal 3L to receive the left-channel audio signal and to supply this audio signal to sampling circuit 5L. As one example, the sampling circuit is a sample-and-hold circuit responsive to sampling signals of frequency f.sub.s produced by pulse generator 10 to produce periodic amplitude samples of the audio signal. These samples are applied to A/D converter 6L which produces a pulse encoded representation, for example, a parallel 13-bit signal, of the analog sample. These parallel bits are supplied to parallel-to-serial converter 7 for serialization. Similarly, the right-channel audio signal is received by an audio input terminal 3R, and low-pass filter 4R, sampling circuit 5R and A/D converter 6R function to supply a 13-bit pulse encoded representation of the right-channel audio signal sample to parallel-to-serial converter 7. Although not shown in detail, it is apparent that the parallel-to-serial converter is controlled by clock pulses applied thereto by pulse generator 10 for producing the 13 serialized bits of one channel, for example, the left channel, followed by the 13 serialized bits of the other channel.

The pulses produced by parallel-to-serial converter 7 are supplied to memory 7 to be written into addressed locations therein in response to write pulses derived from pulse generator 10. In a preferred embodiment described below, the memory is a RAM and each pulse is stored in a separately addressed location. Thus, the block designated "memory" also includes suitable control circuitry.

Since the sampling rate f.sub.s is less than the signal recording frequency f.sub.t, memory 8 functions to vary the time domain of the pulse signals so as to adapt the pulse signals for recording. That is, these pulse signals are subjected to a time-compression operation. To this effect, the pulse signals previously stored in memory 8 are read out from their addressable locations in response to read pulses derived from pulse generator 10, and then supplied through a mixer circuit 9 to VTR 1. The purpose of the mixer circuit is to add the usual video synchronizing signals to the pulse signals read out of memory 8, thereby enabling VTR 1 to be controlled in its operation in the usual manner, which is known to the television art and need not be explained herein.

Pulse generator 10 is a timing circuit to which reference clock pulses, such as produced by reference oscillator 11, are supplied, these reference clock pulses being used to generate the aforementioned sampling pulses, converter control pulses, memory write and read pulses, and video synchronizing pulses.

The format in which the pulse encoded audio signals are recorded by VTR 1 is shown in FIG. 2A. One complete frame is shown as being comprised of an even field followed by an odd field, the fields being separated by the vertical blanking interval, as is conventional for a video signal. This vertical blanking interval usually includes 10 or 10.5 horizontal line intervals which are provided with no video information, then a period of equalizing pulses occupying 3 horizontal line intervals, then a period of vertical synchronizing pulses occupying another 3 line intervals, followed by another period of equalizing pulses and 1.5 or 1 line intervals which are provided with no video information. Thus, a conventional video signal has a vertical blanking interval of 20horizontal line intervals. The duration defined by the first 10 or 10.5 line intervals in the vertical blanking interval is used by VTR 1 for head switch-over; that is, switching from one rotary head to the other. Usually, the second set of equalizing pulses is used to define the video retrace interval. However, when VTR 1 is used to record audio information, this second set of equalizing pulses is not necessary. Hence, the vertical blanking interval can be shortened by three line intervals, thus extending the time during which useful information (i.e., audio information) can be recorded.

Therefore, as shown in FIG. 2A, the pulse encoded audio signals are recorded in an "even" field in a slant track by VTR 1, followed by a vertical blanking interval formed of 10.5 line intervals followed by 3 line intervals of equalizing pulses and 3 line intervals of vertical synchronizing pulses and then 1 line interval. Succeeding this vertical blanking interval is the "odd" field of pulse encoded audio signals, followed by a vertical blanking interval formed of 10 line intervals, then 3 line intervals of equalizing pulses, 3 line intervals of vertical synchronizing pulses and then 1.5 line intervals. In both the "even" and "odd" fields, the pulse signals are recorded as 735 successive words, each word being formed of 26 bits to represent the left and right channel samples, and 3 words being provided during each horizontal line interval. While these words are recorded similarly in each field, the "even" field of pulse data follows the vertical synchronizing pulses by 1.5 line intervals, while the "odd" field of pulse data follows the vertical synchronizing pulses by 1 line interval.

As shown in greater detail in FIG. 2B, successive words are separated by synchronizing pulses H.sub.D. These synchronizing pulses resemble horizontal synchronizing pulses, but are of three times the horizontal synchronizing frequency f.sub.h. Synchronizing pulses H.sub.D are of a duration equal to two data bits and are of a period that is one-third the line interval. The synchronizing pulses are produced by pulse generator 10 as aforesaid, and are less than the pulse amplitude of the pulse encoded audio information. In one example the ratio of synchronizing pulse level H.sub.D to data pulse level is 3:7, with the synchronizing pulses being negative. For the purpose of simplification, the pulse data shown in FIG. 2B is assumed to be formed of alternating 1's and 0's.

In a conventional video signal, the equalizing pulses are negative and are twice the frequency of the horizontal synchronizing pulses. The vertical synchronizing pulses also are twice the frequency of the horizontal synchronizing pulses, but are positive. Consistent with this video signal format, the equalizing pulses here recorded on VTR 1 are negative and are twice the frequency of the synchronizing pulses H.sub.D ; while the vertical synchronizing pulses are positive and are twice the frequency of synchronizing pulses H.sub.D, as shown in FIG. 2C. The width of each equalizing pulse is equal to 1-bit width, and the width of each vertical synchronizing pulse is equal to 2-bit widths.

The signal format of the pulse encoded audio signals, as shown in FIGS. 2A-2C, is very similar to that of a conventional video signal and, therefore, readily can be recorded by VTR 1. That is, the VTR includes servo control apparatus which is responsive to the vertical synchronizing signal for controlling the rotation of the magnetic heads and the movement of tape and time-base error correcting circuitry which is responsive to the horizontal synchronizing signal to correct for time-base error during signal playback. This apparatus and circuitry likewise respond to the vertical synchronizing signals and synchronizing pulses H.sub.D which are provided with the pulse encoded audio signals, as shown in FIGS. 2A-2C.

In view of the foregoing, if the pulse signals were recorded at the same rate at which they are produced, the fact that the audio signal is continuous means that there would not be any available interval to insert the aforementioned vertical synchronizing signal. Rather, a portion of the audio information would have to be replaced by the vertical synchronizing signal, thus degrading the quality of the audio information which is reproduced. However, since time compression of the pulse signals is achieved by the operation of memory 8, a suitable interval is provided within which the vertical synchronizing signal can be inserted without impairing the audio information.

Returning to FIG. 1, after the aforedescribed pulse-encoded audio signal is recorded by VTR 1, it may be reproduced subsequently. For this purpose, the reproducing channel is shown connected to an output terminal 2.sub.0 of the VTR. This reproducing channel may be in combination with the illustrated recording channel, or it may form separate apparatus. In addition to memory 16, serial-to-parallel converter 17, D/A converters 18 and low-pass filters 19, described above, the reproducing channel also includes a filter 12 coupled to VTR output 2.sub.0 for removing noise components in the reproduced pulse signals, a wave shaping circuit 13 coupled to filter 12 for reshaping the pulse signals, a synchronizing signal separator circuit 14 coupled to wave shaping circuit 13 for separating the synchronizing signals from the reproduced pulse signals, and a data extracting circuit 15 coupled to separator circuit 14 for passing, or transmitting, the data pulses to memory 16. A pulse generator 21 is coupled to separator circuit 14 for sensing the synchronizing signals and for generating various timing signals in response thereto. As illustrated, these timing pulses are applied to data extracting circuit 15, memory 16, serial-to-parallel converter 17 and D/A converters 18.

In operation, VTR 1 reproduces the pulse signals recorded in the slant tracks, as shown in FIGS. 2A-2C, at the same rate as the signal recording rate. Synchronizing signal separator circuit 14 and data extracting circuit 15 remove synchronizing pulses H.sub.D and those pulses in the vertical blanking interval occupying the 17.5 horizontal line intervals, illustrated in FIGS. 2A and 2C. The resultant pulse data signal thus includes a gap