A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, the cache memory control determines if the addressed data is present in the cache memory. If so, the data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache memory, the cache memory control gains access to the bus by a priority circuit and reads out the data from memory, storing the data in the cache memory at the same time that it transfers the data to the processor. If the memory request by the processor is to write data in memory, the cache memory control gains access to the bus and initiates a data store in the main memory. At the same time, the cache memory control determines if the existing data being overwritten at the addressed location in main memory is present in the cache memory. If so, it updates the data in the cache memory at the same time it writes the data in main memory.
A tightly coupled computer system which provides for data coherency and includes an addressable main memory for storing blocks of data, a plurality of processors for accessing the blocks of data, each of the processors having an addressable cache memory for storing a number of blocks of data, a bus for intercoupling the plurality of processors with the addressable main memory and for intercoupling each of the plurality of processors with any other of the plurality of processors, and wherein only one of the plurality of processors and addressable main memory is a current owner of an address of a block of data, wherein the current owner has the correct data for the owned address, and wherein the ownership of an address is dynamically changeable among the addressable main memory and the plurality of processors.
In a multiprocessory system comprising a plurality of CPUs interconnected by a common bus, means are provided whereby the CPUs are periodically and cyclically enabled to access the bus. Data transfer from one CPU to another is performed by first storing the data into a main memory connected to the bus, then transferring the data from main memory to the destination CPU when the latter is enabled to utilize the bus and is in a condition to accept the data. Means can also be provided whereby, when data must be immediately transferred from one CPU to another, the sending CPU stores the data in main memory, generates signals whereby the destination CPU is given use of the bus, and generates an interrupt which causes transfer of the stored data into the destination CPU.
A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and shared memory. Bus snooping capabilities are enabled by a stand-alone bus snooping device connected to the bus and the caching device or by bus snooping functions incorporated into the caching device. The bus snooping device monitors communications on the bus and causes invalidation of cached information to maintain cache coherency before the communications complete.
A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).
A computer constructed in accordance with the invention includes at least one transmitting and two receiving structural components. At least the receiving structural components are connected with one another by connecting lines that are arranged in parallel with one another. These connecting lines include data lines and also addressing lines by which each of at least the receiving structural components can be uniquely addressed. When addressed by the appropriate addressing signal, the respective receiving structural component reads the data that is then present at the data lines. A decoder is provided in the transmitting structural component. This decoder is operative for decoding the addressing lines which respectively address the receiving structural components in such a manner that simultaneous addressing of several structural components is possible. The receiving structural components are connected with one another and with the transmitting structural component by a common feedback line.
