An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAM's), which may be written into, or read from in conventional fashion. In a recognition mode, information is read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor. In accordance with specific aspects of the present invention, masking and/or multiwrite features are provided to permit bit reading/writing/searching, rapid memory writing, to facilitate logical and arithmetic data processing and the like.

An associative memory system including a plurality of associative data controllers (ADCs) which operate in parallel upon a mass storage including a storage array for each ADC. A primitive function processor (PFP) couples the ADCs to a control unit which provides user access to the system. Hardware instructions are issued by the PFP to the ADCs to enable them to operate in parallel. The ADCs have circuits for performing simultaneous read/write operations with their related storage arrays, and for performing tagging operations, minimum/maximum operations, and logical operations.

A hybrid associative memory has a non-associative basic storage and an associative surface. Every data unit individually selectable in the basic storage is sub-divided into sub-units, and a logic unit ALV of corresponding working capacity is provided in the associative surface for every sub-unit. In order for either the sub-units of a data unit or the respectively corresponding sub-units of a corresponding plurality of data units to be connected through to the associative surface as a data unit, the storage of the data units in the basic storage is divided into areas. Every area is formed of a plurality of data units corresponding in number to the plurality of sub-units of the data unit. The sub-units of all data units of an area are ordered in offset fashion therein in accordance with a prescribed classification pattern. The access to a data unit is internally controlled via an address re-ordering unit for the row address in the address controller. The re-ordering of the sub-units within the respective data unit, required to produce the required sequence, is controlled by means of corresponding data reordering units.