A method of producing a highly reliable mask ROM and the product produced by the method are disclosed. The method is characterized by comprising the steps of forming low doped source-drains to relax the electric field between the gate electrode and drain, thereby suppressing the creation of hot carriers, and of depositing dielectrics of a predetermined thickness between neighboring gates to control the projection range of impurities implanted into the source-drain region of the bit into which data is to be written, the thickness of the dielectrics being determined such that the projection range does not exceed the junction depth of the source-drain in order to preclude the formation of parasitically doped layers which cause punch-through across an unwritten transistor.

A contact chain structure, for troubleshooting integrated circuits of EPROM memories, of a type comprising cluster contacts connecting metallization layers to active areas of the circuit, comprises a source-drain region implanted centrally of each active area. Deposited over that region is a gate region which, on being biased, enables the conductive condition of the chain to be varied.

An integrated circuit structure includes a substrate, diffused regions formed in the upper surface of the substrate, and thin and thick insulative regions, polycrystalline regions, and metallic interconnections selectively formed overlying selected areas of the substrate surface. An insulating passivation layer overlying the integrated circuit provides mechanical protection for the integrated circuit. Openings are selectively formed in the passivation layer overlying a portion of the integrated circuit at a position other than that of a bonding pad, and above one of the polycrystalline regions positioned over one of the thin insulating regions. The openings may be used to perform ion implantation to modify theelectrical characteristics, such as the threshold voltage, of the integrated circuit at those locations. The disturbance produced in the lattice structure of the silicon substrate during selective ion implantation may, in one aspect of the invention, not be annealed out in subsequent processing steps such that the remaining lattice disturbance further modifies the threshold voltage at the selected implanted locations.

Apparatus for decoding multiple input lines includes a line selector and a line deselector. The line selector is capable of receiving a plurality of closely spaced input lines and simultaneously decoding the input lines into at least one output line having an effective pitch which can be arbitrarily greater than the pitch of the input lines. An array of MOS transistors is formed in the line selector to decode the input lines while increasing the output pitch relative to the input pitch. Similarly, the line deselector receives the same plurality of input lines and insures that deselected lines are connected to an appropriate voltage potential in order to prevent them from "floating".

A flat-cell ROM array reduces the number of block select transistors utilized, allows for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieves very high density and high performance. Parallel buried diffusion regions are deposited in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between the respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines, and a plurality of metal bit lines and virtual ground lines is deposited. These metal lines are shared by even and odd columns of field effect transistors. Access to the metal lines is made through a plurality of LOCOS block select transistors connected to every other buried diffusion bit line. The alternate buried diffusion bit lines are connected through either a buried diffusion region to its left or a buried diffusion region to its right to the metal lines, by means of bank right and left select transistors.