The specification shows and describes a visual display of the CRT variety wherein column separator lines may be displayed intermediate character matrix positions as an operator aid. The visual column separators further do not require that any character position be used or encroached upon and where limited spacing occurs between character forming dot matrices, logic delays may be utilized in the video modify circuitry to displace the separator line and thereby visually distinguish such separator line from any adjoining character.
An alignable electronic background grid generation system, for use with a raster-type video graphics display unit on which graphic data is displayed, includes a horizontal grid line generator and a vertical grid pattern controller. An appropriate control device supplies to these components background grid parameter data including line spacing, line intensity pattern, and line offsets. Utilizing this data, the generator produces, in synchronism with horizontal video scanning of the display unit, grid intensity control signals indicating the requisite intensity of background grid spots at corresponding picture elements in the resultant display. These intensity control signals are modified in response to the output of the vertical grid pattern controller, which itself is synchronized to the vertical line clock of the video graphics display unit. The supplied grid parameter data can be altered as the location or size of the displayed graphic data is changed, so that the resultant background grid will remain aligned with the displayed graphic data.
A display system having a scanned CRT provides a full screen layout of alphanumeric characters and at least one additional screen layout, e.g. a split screen layout. A refresh buffer stores data to be displayed in a first sequence of addresses so that when this data is read out by address generator in the first sequence a full screen layout results. A read only translation store may be selectively addressed by the first sequence of addresses to provide a modified sequence of translated addresses. When the refresh buffer is addressed by the sequence of translated addresses, a split screen layout of the data results. A selector is operable to address the refresh buffer with either the first sequence of addresses or the sequence of translated addresses. Logic inhibits character display in a blank area between the two halves of the split screen. Attribute decode logic enables different attributes to control screen halves during split screen operation. Read only store is preferably replaced by a read/write store when several alternative screen layouts are required. Each alternative screen layout requires a sequence of translated addresses to be supplied to the read/write store from a controller.
Since the present invention includes a character pattern ROM 7a having no memory of upper and lower space data lines, there is an address determination circuit 28 and a selection circuit 29, and when a value of an address signal L is not within an actual memory range from "3" to "16", the address determination circuit outputs a false signal as a determination result upon which the selection circuit outputs character pattern lines each including only extra space data, so that it is possible to serve a similar function to that of a conventional one with a smaller memory capacity than that of the conventional one.
A composite signal is transmitted via a transmission line to an x, y, z display device. The composite signal contains in each of a plurality of predetermined time intervals an identifiable signal. The first signal of said composite signal is a synchronizing start signal. The other signals contain varying information. In the display device there are generated an x-, a y- and a z-coordinate signal. These coordinate signals are generated such that in said predetermined time intervals with reference to the synchronizing start signal and in predetermined varying combinations two of these three coordinate signals are developed and determined by the display device, whereas the remaining third coordinate signal is developed by the display device, but is determined from one of the other signals of the composite signal received via the transmission line.
A normal video signal and an overlay video signal are combined by supplying the normal video signal to the base of a first emitter follower transistor while the overlay video signal is supplied to the base of a second emitter follower transistor. The two transistors are biased such that the first transistor is at a slightly lower voltage than the second (overlay) transistor and is reversed biased (off) any time data is available from the overlay video signal.
