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Claims  |
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What is claimed is:
1. A device for detecting a key switch operation comprising:
a key switch matrix circuit including a plurality of key switches arranged
in rows and columns, said rows representing respective blocks of the key
switches;
first means for detecting simultaneously all blocks in which key switches
in operation exist;
second means for simultaneously detecting all columns in a single one of
said detected blocks on which the key switches in operation are disposed,
said column detecting being carried out for one block after another, for
each of the separate blocks detected by said first means; and
control means for causing said second means to implement the column
detection for one block at a time with respect to each of the blocks
detected by said first means;
each of said key switches in operation being identified by a combination
key code designating the single detected block and the column on which
said key switch in operation is disposed.
2. A device for detecting a key switch operation as defined in claim 1
which further comprises:
third means including block memory means for storing signals indicative of
the blocks detected by said first means, and block extraction means for
extracting one by one in sequence the detected block-indicative signals
stored in said block memory means; and
fourth means including note memory means for temporarily storing signals
indicating the columns which contain key switches in operation in each
block detected by said second means, and column extraction means for
extracting the temporarily stored column indicating signals one by one in
sequence;
whereby the key switches in operation are detected one by one in sequence.
3. A device for detecting a key switch operation as defined in claim 2
which further comprises:
means for producing block code signals representing the blocks extracted by
said block extraction means; and
means for producing note code signals representing the columns of the key
switches in operation extracted by said column extraction means;
whereby key codes identifying the key switches in operation are
sequentially produced by said means for producing block and note codes.
4. A device for detecting a key switch operation as defined in claim 3
wherein said first means comprises:
a first signal delivery circuit for supplying signals to said matrix
circuit in parallel via conductors corresponding to columns, said supplied
signals passing through the respective key switches in operation and
leaving the matrix circuit via conductors corresponding to the blocks; and
a block detection circuit responsive to the signals supplied by said first
signal delivery circuit for simultaneously detecting in a certain period
of time all the blocks in which the key switches in operation exist;
wherein said second means comprises:
a second signal delivery circuit for supplying signal to said matrix
circuit via the conductor corresponding to a single one of the detected
blocks, said signal going through the operated key switches in said single
block and leaving the matrix circuit in parallel via the conductors
corresponding to rows containing operated key switches in that single
block; and
a column detection circuit responsive to the signals supplied by said
second signal delivery circuit for simultaneously detecting all notes of
the key switches in operation in said single block, said fourth means
being connected to said column detection circuit;
wherein said third means comprises a circuit for operating said second
signal delivery circuit every time one of the blocks is extracted; and
wherein said control means comprises a control circuit which performs the
control operation in such a manner that whenever said column extraction
means has completed extraction of all column indicating signals of one
block, said block detection circuit extracts a next block.
5. A device for detecting a key switch operation as defined in claim 1
which further comprises means for producing a finish signal when detection
of all of the key switches in operation has been finished.
6. A device for detecting a key switch operation in which key switches in a
matrix are connected at row conductor and column conductor terminals
thereof to a circuit for detecting the operation of the key switches,
comprising:
capacitance elements provided between each matrix row and column conductor
and ground;
first charging-discharging means for charging or discharging the
capacitance elements provided on the row conductor terminals so that the
charge-discharge condition of each such capacitance element indicates
whether at least one switch in the corresponding matrix row is in
operation;
second charging-discharging means for charging or discharging the
capacitance elements provided on the column conductor terminals only
through the key switches in operation in one of the matrix rows in which
there is at least one switch in operation, as indicated by the
charge-discharge condition of said capacitance element on the
corresponding row conductor terminal; and
detection means responsive to the charge-discharge condition of each
capacitance element on the column conductor terminals, as caused by said
second charging-discharging means, for detecting which columns in said one
matrix row contain key switches in operation.
7. A device for detecting a key switch operation as defined in claim 6
which further comprises:
separate detection means responsive to the charge-discharge condition of
the capacitance elements provided on the row conductor terminals caused by
said first charging-discharging means;
memory means for storing signals representing the charge-discharge
conditions detected by said two detection means separately on the side of
the row conductor terminals and on the side of the column conductor
terminals; and
means for sequentially extracting and codifying only the signals stored in
said memory means.
8. A system for detecting actuated key switches in a matrix, comprising:
source means for providing signals in parallel to all columns of said
matrix,
a block memory having a storage cell associated with each row of said
matrix, said block memory storing the signals received from said source
means via said matrix so as to indicate which rows contain at least one
actuated switch,
single block extraction means for reading out row-indicating signals stored
in said block memory one at a time, in sequence, and for providing a
signal to said matrix along the single row corresponding to the currently
read-out row-indicating signal,
a note memory having a storage cell associated with each column of said
matrix, said note memory storing signals received from said block
extraction means through said matrix so as to indicate which columns in
said single row contain actuated switches,
note extraction means for reading out column-indicating signals from said
note memory one at a time, in sequence, each such read out
column-indicating signal and the concurrently read out row-indicating
signal together uniquely identifying a corresponding actuated switch in
said matrix, and
timing control means connected to said block extraction means and to said
note extraction means, for causing said single block extraction means to
read out the next sequential row-indicating signal only after all of the
column-indicating signals for said single row have been read out by said
note extraction means.
9. A system for detecting the operation of individual switches in a matrix,
comprising:
a matrix of row conductors and column conductors, each switch being
connected at an intersection of said matrix, there being a capacitance
between each conductor and ground,
first means for precharging all of the capacitances of each column
conductor, whereby the capacitance of each row conductor which is
connected to any column conductor by at least one closed switch will be
initially charged,
second means for subsequently charging all of said row conductor
capacitances except one that was previously charged by said first means,
said one row capacitance being discharged, whereby all of said column
capacitances for column conductors that are connected to said one row
conductor by a closed switch will be discharged, all other column
capacitances remaining charged, and
means, responsive to the resultant charge condition of said row and column
capacitances, for uniquely indicating the matrix position of closed
switches in said matrix.
10. A system according to claim 9 further comprising:
encoder means for producing encoded signals identifying the specific column
conductors having discharged capacitances, and
control means, responsive to completion of read-out by said encoder means,
for causing said first means again to precharge all of said column
conductor capacitances, and for causing said second means to charge all of
said row conductor capacitances except another one that was initially
charged by said first means, whereby all of said column capacitances for
column conductors that are connected to said other row conductor by a
closed switch will be discharged, all other column capacitances remaining
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to a key switch operation detection device capable
of efficiently detecting operations of a number of key switches.
Various proposals have been made for detecting an operating state(making or
breaking) of one or more key switches provided in a device such as a
keyboard of an electronic musical instrument which has a large number of
key switches.
There is a conventional device in which conductors are individually
connected to respective key switches and outputs delivered on these
conductors are individually detected. This device requires a complicated
wiring and therefore is uneconomical. Besides, this device requires a
large number of connection terminals for connecting such wiring to a
circuit utilizing the result of detection of the key switch states so that
it is unsuited for a circuit design employing a semiconductor integrated
circuit in which the number of connection pins available for use is
limited.
There is another proposal according to which key switches are arranged in a
matrix circuit so that each of these key switches will be identified by a
column line (input line) and a row line (output line) on which the key
switch is disposed and an operating state of each key switch is detected
by sequentially scanning all of the key switches. Such proposal is
disclosed in the issued U.S. Pat. No. 3,882,751. The proposed device is
advantageous in that the number of conductors to be connected between the
outside circuit and the key switches can be saved. This device, however,
has a problem that an undesirable time delay sometimes occurs between the
actual making or breaking of the key switches and detection thereof
because all of the key switches must be scanned one by one. Further, time
required for detecting the states of all of the key switches is fixed
depending upon the scanning speed so that if there are only a few key
switches in operation among a large number of key switches, a substantial
waste of time occurs due to the fixed time for detection. To reduce such
waste of time, the rate of the clock used in the system must be increased
with resulting adverse effects on the system such as increase in the power
consumption.
With a view to improving the disadvantages in the above described proposal,
the applicant has proposed novel key switch detection systems in its
issued U.S. Pat. No. 3,899,951 and copending application Ser. No. 602631
now U.S. Pat. No. 4,033,221. These systems basically depend upon scanning
of a key switch matrix circuit to detect the operating or nonoperating
state of the key switches and the improvement resides in providing a
device for reducing the scanning time by scanning only necessary sections
from among all the key switches. Such improvement has succeeded only in
reduction of the scanning time, but yet the unavoidable waste of time
inherent in the scanning systems has remained unsettled. Even if the
scanning section is limited only to necessary section(s) in the above
scanning systems, the probability that the switches in a nonoperating
state are included in the scanning section(s) is fairly high. Accordingly,
such nonoperating key switches must be equally scanned and waste of time
still occurs.
Furthermore, if a low rate clock is desirable in a circuit utilizing the
result of detection of the key switches for reasons of simplification of
the circuit design, reduction of power consumption and reduction of
manufacturing costs, the above described waste of time accompanying the
scanning system must be eliminated. The prior art scanning system
apparently has limitations in eliminating such waste of time.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to reduce time required for
detecting the operation of the key switches to a maximum possible extent.
According to the present invention, each of a number of key switches is
connected at one terminal thereof (e.g. a terminal on a movable contact
side) to a first detection circuit and at the other terminal thereof (e.g.
a terminal on a stationary contact side) to a second detection circuit. In
one detection operation mode, signals are applied from the first detection
circuit to the second detection circuit in parallel through the key
switches to enable the second detection circuit to perform a necessary
detection operation. In another detection operation mode, signals are
applied from the second detection circuit to the first detection circuit
in parallel through the key switches to enable the first detection circuit
to perform a necessary detection operation. The operating or nonoperating
state of the key switches is detected in accordance with results of the
detection operation in the first and second detection circuits.
The detection operation includes storage of signals and the signals are
passed through key switches in operation and stored in the first or the
second detection circuit. Checking of the respective key switches is made
simultaneously in parallel and only signals having passed through the key
switches in operation are stored in the first or the second detection
circuit. If the object of detection is making of a key switch "the key
switch in operation" means a key switch which is ON and if the object of
detection is breaking of a key switch, "the key switch in operation" means
a key switch is OFF.
Describing the basic concept of the present invention more specifically, a
number of key switches are divided into blocks and block codes (block
identifying codes) are assigned to the respective blocks for identifying
each block, whereas note codes (note identifying codes) are assigned to
the respective key switches in each block for identifying each key switch.
A common note code is assigned to key switches of the same note regardless
of blocks to which the key switches belong. The key switches can be
individually identified by key codes which are combinations of the block
codes and the note codes. The key switches of the same note are commonly
connected at one terminal thereof to constitute respective note lines
which in turn are connected to a note detection circuit (i.e. the first
detection circuit) while the key switches of the same block are commonly
connected at the other terminal thereof to constitute respective block
lines which are connected to a block detection circuit (i.e. the second
detection circuit).
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 and 2 are block diagrams schematically showing the basic
construction of the device according to the invention;
FIG. 3 is a block diagram showing an embodiment of the invention in
connection with a key switch circuit and a note detection circuit;
FIGS. 4(a) and 4(b) are block diagrams showing the same embodiment in
connection with a block detection circuit;
FIG. 5 is a diagram showing how each key switch is identified by a block
and a note;
FIG. 6 is a diagram illustrating symbols used for designating logical
circuits;
FIG. 7 is a block diagram showing an example of a device for generating
mode signals designating various detection operation modes;
FIGS. 8(a) through 8(n) are timing charts for explaining operations of the
component parts shown in FIGS. 3 and 4;
FIG. 9 is a schematic block diagram showing another embodiment of the
invention in connection with a key switch circuit;
FIG. 10 is a schematic block diagram showing still another embodiment of
the invention in connection with a key switch circuit;
FIG. 11 is a block diagram showing a different example of the note
detection circuit producing a start code;
FIG. 12 is a block diagram showing an operation control circuit relating to
the modified embodiment; and
FIGS. 13(a) through 13(e) are timing charts for explaining production of
control pulses used in the circuit shown in FIG. 12.
DESCRIPTION OF PREFERRED EMBODIMENTS
As shown in FIG. 1, conductors n.sub.1 -n.sub.n (note lines) representing
respective notes are connected to terminals 1a (movable contacts) disposed
on one side of each key switch in a key switch group 1, whereas conductors
b.sub.1 -b.sub.m (block lines) representing respective blocks are
connected to terminals 1b (stationary contacts) disposed on the other side
of each key switch in the key switch group 1. The conductors n.sub.1
-n.sub.n are connected to a note detection circuit 2 and the conductors
b.sub.1 -b.sub.m to a block detection circuit 3. Accordingly, the total
number of the conductors connected to the key switch group 1 is much less
than the total number of the key switches. If the total number of the key
switches in the present embodiment is represented by n .times. m, the
total number of the conductors required is only n + m.
Detection of all of the key switches is completed by implementation of
several different detection operation modes (hereinafter briefly referred
to as "operation mode" or "mode").
In the first one of these modes, a signal is supplied from a signal source
21 of the note detection circuit 2 to all the key switches in parallel via
the conductors n.sub.1 -n.sub.n. The signal is passed only through the
closed contact of the key switch or key switches in operation to a
corresponding one of the conductors b.sub.1 -b.sub.m. The detected signal
(i.e. from which conductor(s) the signal(s) are delivered) is stored in a
block memory 31 of the block detection circuit 3. By this arrangement, the
block or blocks in which the key switch or switches in operation exist are
detected. The timing of the storing of the detected key switches is in
synchronization with a first mode signal S.sub.1 designating the first
mode.
In the second mode, a single block among the block or blocks stored in the
memory 31 is extracted by a single block extraction unit 32 and thereupon
a signal is applied through one of the conductors b.sub.1 -b.sub.m
corresponding to the extracted block to the stationary contacts of the
respective key switches of the extracted block. The signal from the block
detection circuit 3 is passed to one or more of the conductors n.sub.1
-n.sub.n connected to the movable contacts of the respective key switches
for notes covered by the extracted block and corresponding to the key
switches in operation. This detected signal (i.e. from which conductor(s)
the signal(s) and delivered) is stored in a note memory 22 of the note
detection circuit 2. Accordingly, which one or ones of the key switches in
the extracted block are in operation is detected. The extracting operation
in the single block extraction unit 32 and the storing operation in the
note memory 22 are performed in synchronization with a second mode signal
S.sub.2 designating the second mode.
In the second mode, key switches which are in operation can be individually
identified by combination of a single block name extracted by the single
block extraction unit 32 and one or more note names stored in the note
memory 22.
It will be understood from the foregoing that one feature of the present
invention is the construction in which the key switches 1 are connected
between the note detection circuit 2 and the block detection circuit 3 and
detection of the key switches 1 in operation is made by transmitting
signals in opposite directions through the key switches 1. According to
the invention, the terminals 1a and 1b of the key switches 1 are not
fixedly used as either input terminals or output terminals but the input
side and output side of both terminals are reversed depending upon the
operation mode, i.e. whether the operation mode is the first mode or the
second mode.
If a circuit (not shown) utilizing the result of detection of the key
switches permits, the output of the single block extraction unit 32 and
the parallel outputs of the respective notes from the note memory 22 may
be directly supplied to the circuit for providing the circuit with the
result of key switch detection. If there are blocks which still remain
stored in the block memory 31 without being extracted by the single block
extraction unit 32, the above described second mode is repeated. More
specifically, upon extraction of a certain block stored in the block
memory 31 and completion of the second mode for that block, another block
stored in the block memory 31 is extracted in response to a next second
mode signal S.sub.2 and the second mode is repeated. In this manner, the
blocks to which the key switches in operation belong and which have been
detected and stored in the memory 31 in the first mode are extracted one
by one in response to the second mode signal S.sub.2. Thus, detection of
all the key switches in operation is completed when the second mode is
completed with respect to all of the Blocks stored in the memory 31.
Assuming, for example, that a pulse width of the mode signals S.sub.1 and
S.sub.2 respectively is 1 clock time, detection of all of the key switches
in operation is completed in only 2 clock times if the key switches in
operation belong to a single block. Even if the key switches are in
operation in all of the blocks, detection of all of the key switches is
completed in "m + 1" clock times (e.g. 13 clock times if m = 12). In the
prior art key scanning systems, time required for detection of all of the
key switches is 144 clock times in a case where n = 12 and n = 12.
For convenience in the circuit utilizing the result of detection of the key
switches, the stored notes in the note memory 22 should preferably be
delivered out one by one in series.
According to the invention, for achieving the above objective, a third mode
is provided for delivering out the note identifying signals of the key
switches in operation from the note memory 22 one by one after the note
identifying signals have been stored in the memory 22.
In the third mode, a single one among the notes (i.e. note identifying
signals) stored in the note memory 22 is extracted by a stored note
extraction unit 23 as shown in FIG. 2 (in which like component parts are
designated by the same reference characters) and a signal representing the
extracted note is applied to an encoder 24 to produce a code signal (note
code NC) consisting of plural bits and representing the note. The
extracting operation in the extraction unit 23 is performed in
synchronization with a third mode signal S.sub.3. This third mode is
repeated in response to the clock of the system unitl the note signals
stored in the note memory 22 have all been extracted by the note
extraction unit 23 and corresponding note code signals have all been
delivered out. Since the third mode is implemented only with respect to
the notes stored in the note memory 22, there is no room for occurrence of
waste of time. If, for example, three kinds of notes are stored in the
note memory 22, the third mode concerning a certain block is completed in
3 clock times. Completion of the third mode can be known by exhaustion of
the contents stored in the note memory 22 due to extraction and, upon
detection of the completion of the third mode, the mode is returned to the
second mode, the single block extraction unit 32 extracting a next stored
block and the note memory 22 memorizing the notes of the key switches in
operation in that block. Then, the third mode is implemented again. In the
third mode concerning a certain block, the signal representing the block
is stored in a memory-and-encoder circuit 33 of the block detection
circuit 3 whereby a code signal (block code BC) consisting of plural bits
and representing the block is produced by the circuit 33. Accordingly, the
key switches in operation are detected by combinations of the block codes
BC and the note codes NC which are generated in synchronization with each
other. The codes of the key switches in operation are produced one by one
in series.
As described above, the operation mode changes from the first mode to the
second mode, third mode (or repetition thereof), second mode, third mode
....... When production of the key codes has been completed with respect
to all of the blocks stored first in the block memory 31 (i.e. when the
third mode has been completed), the contents of storage in the block
memory 31, have all been extracted and the operation mode now enters a
fourth or stand-by mode. After detection of the stand-by mode, the
operation mode returns to the first mode and the above described detection
operation is repeated. By repetition of the first to the fourth modes,
detection of all of the key switches in operation is carried out from time
to time.
According to the invention, not only key switches which are turned ON, but
also those which are turned OFF may be detected by a construction similar
to the above described one. Such construction may be achieved, for example
by inverting polarity of signals which are applied to or delivered from
the detection circuit 2 and 3 through the key switch group 1, or by
employing break contact type switches as the key switches.
One example of the device embodying the invention will now be described
with reference to FIGS. 3 through 9.
FIG. 3 shows an example of a key switch circuit 10 and a note detection
circuit 20. FIG. 4 shows an example of a block detection circuit 30
connected to the key switch circuit 10 shown in FIG. 3.
A number of key switches KS corresponding to the respective keys on the
keyboard of the electronic musical instrument are provided in the key
switch circuit 10. These key switches are commonly connected block by
block with respect to the blocks U.sub.1 -U.sub.5, L.sub.1 -L.sub.5 and
P.sub.1, P.sub.2 at one input terminal thereof (stationary contact) and
connected to block input-output terminals T.sub.1 through T.sub.12 vis
conductors (block lines) b.sub.1 -b.sub.12. The key switches are connected
at the other terminal thereof (movable contact) to dodes DD and commonly
connected by each note of C.music-sharp., D, .... A.music-sharp., B and C.
Each of the commonly connected key switch groups is connected to
corresponding one of note input-output terminals H.sub.1 -H.sub.12 via
connectors (note lines)n.sub.1 -n.sub.12.
In the present embodiment, the key switches are divided by blocks according
to octave ranges of the keyboard so that the notes in each block literally
express the actual note names of the keys. Let us assume that, as shown in
FIG. 5, twelve keys of C.music-sharp..about.C are assigned to one octave
range from the lowest note side and that the upper keyboard UK comprises
61 keys of a note C of 0th octave through a note C of the fifth octave,
the lower keyboard LK comprises 61 keys in the same manner and the pedal
keyboard PK comprises 25 keys of a note C of the 0th octave through a note
C of the second octave.
Accordingly, the blocks U.sub.1 -U.sub.5 are assigned to the octave ranges
of the upper keyboard UK, the blocks L.sub.1 -L.sub.5 to the octave ranges
of the lower keyboard LK and the blocks P.sub.1, P.sub.2 to the octave
ranges of the pedal keyboard PK, respectively. Consequently, the notes
C.music-sharp. - C in each of the blocks correspond to the note names in
the respective octave ranges. In FIG. 3, connections of the key switches
are shown in detail with respect only to the block U.sub.5 (i.e. key
switches for the fifth octave of the upper keyboard UK) and the block
P.sub.1 (i.e. key switches for the 0th and the first octave of the pedal
keyboard PK). The key switches of the other blocks U.sub.4 -P.sub.2 are
likewise connected to the respective conductors n.sub.1 -n.sub.12 for the
respective notes C, B, A.music-sharp. ...., C.music-sharp. and also to
conductors b.sub.2 -b.sub.11 corresponding to these blocks. As will be
apparent from FIG. 5, since the 0th octave includes only one note of C,
the note C of the 0th octave (designated here as Co) is incorporated in
the blocks U.sub.1, L.sub.1 and P.sub.1 for the first octave. Accordingly,
a key switch of the note Co is additionally included in each of the blocks
U.sub.1, L.sub.1 and P.sub.1. The key switches of the note Co are commonly
connected and further connected to a note input-output terminal H.sub.13
through a conductor n.sub.13 so that the note Co can be distinguished from
the note C.
Since the keyboard portion (the key switch circuit 10) is spaced away from
the electric circuit portion (the detection circuits 20, 30), relatively
long wiring is required for the conductors n.sub.1 -n.sub.13 and b.sub.1
-b.sub.12 connecting the key switch circuit 10 to the note detection
circuit 20 and the block detection circuit 30, and conductor capacitances
C.sub.b, C.sub.n are observed. For convenience of explanation, conductor
capacitance on the block side conductors b.sub.1 -b.sub.12 is all
designated by the same reference character C.sub.b and conductor
capacitance on the note side conductors n.sub.1 -n.sub.13 is all
designated by reference characters C.sub.n. It should be noted, however,
that conductor capacitance observed on one of the conductors b.sub.1
-b.sub.12 and n.sub.1 -n.sub.13 is different from one observed on another.
The present embodiment is so constructed that the conductor capacitances
C.sub.b and C.sub.n are positively utilized.
The note detection circuit 20 (FIG. 3) is composed of signal delivery
circuits 21-1 through 21-13 corresponding to the signal source 21 (FIGS. 1
and 2) and being provided respectively for the note C, B, .....
C.music-sharp. and Co, detected note memory circuits 22-1 through 22-13
corresponding to the note memory 22 (FIGS. 1 and 2) and a note code
production circuit 240 corresponding to the encoder 24 (FIG. 2). As to the
respective circuits 21-1 through 21-13, 22-1 through 22-13 and 23-1
through 23-13, only the circuits 21-1, 22-1, 23-1, 21-13, 22-13 and 23-13
concerning the notes C and Co are illustrated in detail but the rest of
the circuits are all of the same construction as these circuits concerning
the notes C and Co.
The signal delivery circuits 21-1 through 21-13 are adapted to apply
voltage V.sub.DD to the note input-output terminals H.sub.1 -H.sub.13 by
switching of transistors TRA provided for each of the notes. The output
from the note input-output terminals H.sub.1 -H.sub.13 are applied to the
detected note memory circuits 22-1 through 22-13.
The block detection circuit 30 (FIGS. 4(a), (b)) is composed of detected
block memory circuits 31-1 through 31-12 corresponding to the block memory
31(FIGS. 1 and 2) and being provided for the respective blocks U.sub.5,
U.sub.4, ..... P.sub.2 and P.sub.1, block priority gate circuits 32-1
through 32-12 corresponding to the single block extraction unit 32 (FIGS.
1 and 2), a block code production circuit 330 corresponding to the
memory-and-encoder circuit 33 (FIG. 2), a block code temporary memory
circuit 331(FIG. 4(b)) for temporarily storing output B.sub.1 * -K.sub.2 *
of the block code production circuit 330, a block code output gate circuit
332 (FIG. 4(b)) for delivering out the temporarily stored block codes in
synchronization with the outputs of the note code production circuit
240(FIG. 3), and signal delivery circuit 34-1 through 34-12(FIG. 4(a)) for
delivering the block signals extracted in a certain priority order by the
block priority gate circuits 32-1 through 32-12 to the note detection
circuit 20 via the key switch circuit 10.
Only the circuits 31-1, 32-1, 34-1, 31-12, 32-12 and 34-12 concerning the
blocks U.sub.5 and P.sub.1 are illustrated in detail but the circuits 31-2
through 31-11, 32-2 through 32-11 and 34-2 through 34-11 concerning the
other blocks are of the same construction as the circuits concerning the
blocks U.sub.5 and P.sub.1. Although the circuits 21-1 through 21-13, 22-1
through 22-13, 23-1 through 23-13, 31-1 through 31-12, 32-1 through 32-12,
34-1 through 34-12 are different from each other, circuit elements (i.e.
AND gates, OR gates etc.) of these circuits are designated by the same
reference characters irrespective of the kind of block or note so long as
such circuit elements perform the same function.
Before describing about operation of the respective circuits, brief
explanation will be made about symbols used in the accompanying drawings.
Inventers are expressed by the symbol shown in FIG. 6(a), AND gate by the
one shown in FIGS. 6(b) and (c), OR gate by the one shown in FIGS. 6(d)
and (e) and delay flip-flops by the one shown in FIGS. (f). An AND gate or
OR gate with only a few input lines is represented by the symbol shown in
FIG. 6(b) or FIG. 6(d) and one with a relatively large number of input
lines is represented by the symbol shown in FIG. 6(c) or FIG. 6(e). In the
symbol shown in FIG. 6(c) or FIG. 6(e), one input line is drawn on the
input side of the AND or OR gate and signal transmission lines are drawn
in such a manner that they cross the input line with each crossing point
of the input line and the signal transmission line transmitting a signal
to the input terminal of the AND or OR gate being marked by a circle.
Accordingly, the logical formula of the AND gate shown in FIG. 6(c) is
X=A.multidot.B.multidot.D, whereas the logical formula of the OR gate
shown in FIG. 6(e) is X=A+B+C.
In the embodiment shown in FIGS. 3 and 4, all the key switches in operation
are detected by implementation of the first to the fourth operation modes
described above. The kind of the operation mode to be implemented is
designated by the mode signals S.sub.0 -S.sub.3. The stand-by mode signal
S.sub.0 designates the fourth mode (stand-by mode), whereas the first
through third mode signals S.sub.1, S.sub.2, and S.sub.3 designate the
first, second and third modes respectively. The minimum width of the
signals S.sub.0 -S.sub.3 in equal to the period of generation of the clock
pulse .phi..sub.A so that the whole instrument operates in synchronism
with the clock pulse .phi..sub.A.
The period of the clock pulse .phi..sub.A can be determined as desired and
set at 24 .mu.s in the present embodiment. Besides this clock pulse
.phi..sub.A, a low frequency clock LC is used for determining a repetition
rate of the key switch detection operation. The period of this clock LC
can be determined as desired and should conveniently be 200 .mu.s-1 ms for
detection of the key switches.
FIG. 7 shows one example of a circuit for generating the mode signals
S.sub.0 -S.sub.3. In a clock edge detection circuit 41, the low frequency
clock LC(of a desired duty factor) is applied to a delay flip-flop
DF.sub.3 for delaying it by one clock (.phi..sub.A) and also to an AND
gate A.sub.9 whereby the pulse rise of the low frequency clock LC is
detected in synchronization with the clock pulse .phi..sub.A. By this
arrangement, a starting pulse (differentiation pulse)TC having a pulse
width equivalent to the period of the clock pulse .phi..sub.A is produced
with a period of the clock LC. Relationship between the clock pulse
.phi..sub.A and the starting pulse TC is as shown in FIGS. 8(a) and 8(b).
In a mode control circuit 42 in FIG. 7, the stand-by mode signal S.sub.0
is produced by an AND gate A.sub.12 when inverted output signals Q.sub.1,
Q.sub.2 of delay flip-flops DF.sub.4, DF.sub.5 are both a signal "1". If
the starting pulse TC is generated during presence of this stand-by mode
signal S.sub.0, i.e. during the stand-by mode, the output of an AND gate
A.sub.14 becomes a signal "1". The signal "1" is applied to the delay
flip-flop DF.sub.4 via an OR gate OR.sub.5 and, consequently, the output
Q.sub.1 becomes a signal "1" one clock (.phi..sub.A) later. Since the
signal Q.sub.2 is still signal "1", an AND gate A.sub.10 is enabled to
produce the first mode signal S.sub.1. Switching from the stand-by mode to
the first mode is thus controlled by the starting pulse TC.
The operation of the embodiment shown in FIGS. 3 and 4 will now be
described with reference also to FIGS. 7 and 8.
In the stand-by mode shown by period t.sub.1 in FIG. 8, the stand-by mode
signal S.sub.0 (FIG. 8(c)) is applied to the signal delivery circuits 34-1
through 34-12 of the block detection circuit (FIG. 4(a)) and thereby
brings the transistors TRB of the circuits 34-1 through 34-12 into
conduction. As a result, wiring capacitance C.sub.b of the block
conductors b.sub.1 -b.sub.12 is discharged.
As the first mode signal S.sub.1 is produced at the period t.sub.2 (FIG.
8(d)), the signal S.sub.1 is applied to the signal delivery circuits 21-1
through 21-13 of the note detection circuit 20(FIG. 3) to bring the
transistors TRA into conduction. This causes voltage V.sub.DD to be
applied to the key switch circuit 10 via the terminals H.sub.1 -H.sub.13
to charge the wiring capacitance C.sub.n of the note conductors n.sub.1
-n.sub.13. The voltage signal (i.e. the charged voltage of the capacitance
C.sub.n) is simultaneously delivered to the conductors of one or more of
the blocks (U.sub.5 -P.sub.1) to which the key switch or switches KS in
operation belong via such key switches and fed from the corresponding
terminals (T.sub.1 -T.sub.12) to the block detection circuit 30 (FIG.
4(a)). Accordingly, a signal "1" is produced only in the terminals among
the terminals T.sub.1 -T.sub.12 corresponding to the blocks in which the
key switches in operation have been detected.
In FIG. 4(a), outputs TU.sub.5 -TP.sub.1 of the terminals T.sub.1 -T.sub.12
are respectively applied to the corresponding ones of the detected block
memory circuits 31-1 through 31-12. More specifically, the signals from
the terminals T.sub.1 -T.sub.12 are applied to AND gates A.sub.1 of the
circuits 31-1 through 31-12. The first mode signal S.sub.1 is also applied
to the AND gates A.sub.1. Accordingly, a signal "1" is stored in a delay
flip-flop DF.sub.1 through the AND gate A.sub.1 and an OR gate OR.sub.1
only in the circuits among the circuits 31-1 through 31-12 corresponding
to the blocks in which the key switches in operation have been detected.
If, for example, the blocks in which the key switches in operation have
been detected are blocks U.sub.5, U.sub.4, U.sub.3 and P.sub.1, a signal
"1" is stored in the flip-flops DF.sub.1 of the circuits 31-1, 31-2, 31-3
and 31-12. The above described first mode is implemented during one clock
of the period t.sub.2.
If a signal | | |
