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Claims  |
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We claim:
1. A high speed system for displaying a video image on a plurality of
variable intensity display devices, said image reproducing a frame of
video information received in raster form from a video source comprising:
(a) video converter means for receiving said video information from said
source and converting it into digital data,
(b) a display buffer memory capable of storing the digital data
representing said video frame,
(c) a video interface receiving said digital data and transmitting it to
said display buffer, said interface including means for sequentially
addressing the storage locations in said buffer memory,
(d) first bus means for connecting said video interface to said buffer,
(e) a display interface for retrieving said digital data from said buffer
and transmitting it to said display devices,
said display interface including address means for extracting the data from
said buffer in a sequence different than the sequence used to store the
data in the buffer,
(f) computer means for controlling the transfer of data between the
interfaces, the display buffer, the converter and the display devices.
2. The system according to claim 1 wherein said computer means includes:
(a) a digital computer and system interface, and
(b) second bus means for linking said video and display interfaces to said
computer via said system interface.
3. The system according to claim 2 wherein said system further includes a
computer interface linking the first and second bus means whereby digital
data may be transferred between the computer and the display buffer
memory.
4. The system according to claim 1 wherein said system further includes a
computer interface linking said computer means and said first bus means
whereby data may be transferred between the computer means and the display
buffer.
5. The system according to claim 1 wherein said video interface also
includes means for receiving data from said display buffer memory via said
first bus means and transmitting it to said converter means,
said system further including a video monitor connected to said converter
means whereby the digital data received by the converter from the video
interface may be reconverted to video information and displayed on said
monitor for previewing purposes.
6. The system according to claim 1 wherein said display buffer is a random
access memory.
7. The system according to claim 1 wherein said converter means includes:
(a) means for producing digital data representative of all or only a
selected portion of said video frame at a selctable conversion rate, and
(b) means for choosing the portion of said frame to be digitized,
said system capable of at least two modes of operation, a first mode
producing a magnified or enlarged image of only a selected portion of said
video frame on said display devices and a second mode reproducing
substantially all of said video frame on said display devices without
enlargement.
8. The system according to claim 7 wherein said means for producing
includes:
(a) vertical means for selecting which raster lines in said frame are to be
digitized,
(b) horizontal means for selecting the portion of each selected raster line
which is digitized, and
(c) clock means for controlling the number of picture elements produced by
said converter for each raster line.
9. The system according to claim 8 wherein the means for choosing includes:
means for controlling the operation of said vertical and horizontal means
to cause said vertical and horizontal means to choose the desired raster
lines and the desired portion of each selected line to be digitized.
10. A high speed system for displaying a video image on a plurality of
variable intensity display devices, said image reproducing a frame of
video information received in raster form from a video source, said system
capable of at least two modes of operation, a first mode producing a
magnified or enlarged image of only a selected portion of said video frame
on said display devices and a second mode reproducing substantially all of
said video frame on said display devices without enlargement, said system
comprising:
(a) video converter means for receiving said video information from said
source and converting it into digital format, said converting means
including means for producing digital data representative of all or a
selected portion of said video frame at a selectable conversion rate,
(b) means for choosing the portion of said frame to be digitized,
(c) a display buffer memory capable of storing the digital data
representing the selected portion of said video frame,
(d) a video interface receiving said digital data and transmitting it to
said display buffer, said interface including means for sequentially
addressing the storage locations in said buffer memory,
(e) first bus means for connecting said video interface to said buffer,
(f) a display interface for retrieving said digital data from said buffer
and transmitting it to said display devices, said display interface
including address means for extracting the data from said buffer in a
sequence different than the sequence used to store the data in the buffer,
(g) computer means for controlling the transfer of data between the
interfaces, the display buffer, the converter and the display devices.
11. A video to digital converter for converting a frame of analog video
information received in raster fashion into digital data suitable for use
in reproducing said frame on a display device comprising:
(a) an analog to digital (A/D) converter receiving said video information
and digitizing it to produce said digital data when enabled,
(b) means for enabling said A/D converter to produce said digital data,
said enabling means causing said analog to digital converter to digitize
all or only selected portions of said video frame at a selectable data
conversion rate,
(c) means for choosing the portion of said frame to be digitized,
said enabling means capable of at least two operating modes, a first mode
producing data for reproducing an enlarged or magnified image of only a
selected portion of said video frame on said display device, and a second
mode producing data for reproducing substantially all of said video frame
on said display device without enlargement.
12. The converter according to claim 11 wherein said enabling means
includes:
(a) vertical control means for selecting the raster lines in said frame
which are to be digitized,
(b) horizontal control means for selecting the portion of each selected
raster line which is to be digitized,
(c) clock means,
(d) gate means for enabling and disenabling said A/D converter responsive
to said vertical and horizontal control means and for controlling the data
conversion rate of said A/D converter responsive to said clock means.
13. The converter according to claim 12 wherein said means for choosing
includes:
(a) manually operable vertical and horizontal joy stick control means for
producing voltages corresponding to the desired starting raster line and
the desired starting picture element on each such line, respectively,
(b) means for digitizing said voltages to produce position data,
(c) means for applying said position data to said vertical and horizontal
control means thereby to cause said control means to select the desired
portion of said frame for digitizing.
14. The converter according to claim 13 wherein each of said means for
digitizing said voltages includes:
(a) a counter,
(b) a digital to analogue converter producing a stick voltage porportional
to the value of said counter, and
(c) a comparator, comparing one of the said joy stick voltages and the
voltage from said digital to analogue converter, said comparator disabling
said counter when the voltages are equal, the value of the counter, upoin
being disabled, producing the desired position data.
15. The converter according to claim 13 wherein each of said means for
applying includes:
(a) a plurality of latches to which said position data is applied,
(b) means for comparing the position data against previous position data
stored in said latches, and
(c) means responsive to said comparison to strobe the new position data
into said latches when said new data differs from the previous data by a
selected amount,
whereby jitter in the display system is substantially reduced by ignoring
small changes in position which do not exceed said selected amount.
16. The converter according to claim 12 wherein said vertical control means
includes:
(a) switch means responsive to said choosing means for producing binary
numbers representative of the desired starting and ending raster lines in
said frame which are to be digitized,
(b) means for counting the raster lines in said frame and producing a
binary number representative of the current line,
(c) means for comparing the current line number against the numbers
produced by said switch means and producing outputs to said gate means
indicative of the occurrence of the selected starting and ending raster
lines.
17. The converter according to claim 12 wherein said vertical control means
includes selectable means for inhibiting said gate means during every
other raster line.
18. The converter according to claim 17 wherein said selectable means
includes a divide by two flipflop which inhibits said gate means during
every other raster line when selected.
19. The converter according to claim 12 wherein said horizontal control
means includes:
(a) switch means responsive to said choosing means producing binary numbers
representative of the starting and ending picture elements of each raster
line to be digitized,
(b) means for counting the picture elements in each line and producing a
binary number representative of the current picture element,
(c) means for comparing the current picture element number against the
numbers produced by said switch means and producing outputs indicative of
the starting and ending picture elements to said gate means.
20. The converter according to claim 19 wherein said horizontal control
means includes selectable means for inhibiting said gate means during
every other clock pulse from said clock means.
21. The converter according to claim 20 wherein said selectable means
includes a divide by two flipflop which inhibits said gate means during
every other clock signal only when selected. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to the field of large video display systems of the
type appropriate for installation at a stadium. Such displays are usually
formed by a large matrix of variable intensity display devices as, for
example, incandescent bulbs, which are driven by a display system usually
computer controlled. The display system receives a video input, such as
the line feed from a network broadcast or a video tape recording and
digitizes the video information into a complete frame of digital data. In
prior systems the digitized data was stored in a computer memory and then
at an appropriate point transferred from memory to the display device.
Computers utilized for such a system include the Digital Equipment
Corporation PDP Series 8. Although such mini computers are relatively
powerful devices, their data transfer rate, as compared in random access
memories, is low. As a result the computer represents a limiting element
in the system with respect to the rate at which data can be digitized and
transferred to the display device thereby limiting the versatility of the
system with respect to other desirable features, such as maintaining
statistics on participants, displaying caricatures, cartoons, or still
photographs of the players.
It is therefore a desirable objective to retain computer control of the
display system but to remove the computer from the data path to the
display board. The PDP computer referred to employs data break cycles to
transmit information to the display board. It does not have time to do the
other tasks as mentioned, such as disk storage input and output,
statistical updating and message inputting in addition to refreshing the
display. Furthermore, when the computer is included in the data path it is
necessary to synchronize the computer to the master clock. This slows down
processor time still further.
It is accordingly an object of the present invention to provide a display
system which is capable of higher speed than prior devices by virtue of
removing the computer from the data path. By so doing the computer is able
to perform a variety of other tasks as indicated. More importantly, it is
possible to obtain a heretofore unavailable display in which a portion of
the video picture being displayed can be enlarged to permit better viewing
thereof. Often this is analogized to "zooming" in the manner permitted by
an adjustable lens in photography. To obtain an enlarged or zoom picture
it is necessary to utilize greater data rates than present systems can
handle. The present invention, by removing the computer from the data
path, is capable of operating at these higher data rates.
Exemplary of prior systems for displaying data on large display devices are
U.S. Pat. Nos. 4,009,335, 3,941,926, and 3,961,365 assigned to the
assignee of the present invention.
PRIOR ART STATEMENT
In accordance with the provisions of 37 CFR 1.97 et seq., applicants state
that the above referenced patents represent the closest prior art of which
they are aware. These patents disclose large video display devices in
which video data is digitized and a complete frame is stored in the memory
of a digital computer. The data is then taken from the computer memory and
transferred to the display board for illuminating the display devices.
In the first mentioned patent a four shades of gray device is disclosed in
which data is transmitted from the computer to the board during a time
window between processing cycles. In the second mentioned patent a device
capable of displaying eight or sixteen shades of gray is disclosed and a
suggestion of employing a random access memory (RAM) is included. See
particularly columns 17 and 18 of U.S. Pat. No. 3,941,926 which
contemplate a system eliminating the computer and substituting a RAM
memory to store the digitized video data. The increase in data handling
rates with this modification is also recognized. In the last mentioned
patent a color display system is disclosed similar to the eight shades
patent which, however, employs parallel data handling systems to generate
information for bulbs of different colors which are clustered to generate
a color display.
SUMMARY OF THE INVENTION
The present invention employs an entirely different system architecture
whereby video data is received through a video interface from a video to
digital converter. The information is stored directly in a high speed
random access memory display buffer and then outputted via display
interface to the display board. The computer is not present in the data
path but does control the system operation through a system interface. A
computer interface is also provided whereby video information stored in
the computer memory or on computer soft ware devices, such as disk
storage, may be inputted to the display buffer for transmission to the
board.
The video converter includes means for digitizing the video signal and for
altering both the size and resolution of the video display thereby to
permit an enlarged display without an appreciable reduction in picture
quality. This is accomplished by utilizing additional lines of video data
in the field from which the picture information is being obtained whenever
an enlarged picture is desired. Thus, for example, in the standard display
mode every other raster line in one field of a two field video frame is
employed. In the zoom mode of the present invention every line of one
field is utilized. The horizontal clock rate is increased during the zoom
mode to maintain the correct aspect ratio.
It is accordingly an object of the present invention to provide an improved
video display system of the type employed in statia which is capable of
high speed operation.
It is another object of the present invention to provide a video display
device which is computer controlled but does not utilize the computer as
the primary storage area for the digitized video information.
A further object of the invention is to provide a versatile video display
system which can display video information, statistics and similar data.
Another object of the invention is to provide a scoreboard display device
capable of enlarging a portion of a video picture which is of particular
interest and which is capable of altering the display size for special
applications as, for example, at a racetrack, while maintaining picture
resolution at an acceptable level.
Other objects and advantages of the invention will be apparent from the
remaining portion of the specification.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and B comprise a schematic block diagram of the display system
according to the present invention.
FIG. 2 is a schematic diagram of the video interface according to the
present invention.
FIG. 3 is a schematic diagram of the timing and control circuits
incorporated in the video interface.
FIG. 4 is an illustration of a frame of video information used to indicate
the various operating modes of the invention.
FIGS. 5, 6 and 7 illustrate the resulting display of the FIG. 4 video frame
in the standard, zoom and wide screen operating modes.
FIG. 8 is a diagram illustrating the manner in which the video data is
utilized in each display mode.
FIGS. 9A and B is a schematic of the video coverter and the display control
according to the invention.
FIG. 10 is a waveform diagram useful in understanding the operation of the
invention.
DETAILED DESCRIPTION
General System Arrangement
Referring now to FIGS. 1A and 1B, the general arrangement of the invention
is illustrated. The system architecture utilizes a common bus technique
for transmitting data between the various interfaces and a computer system
20 which controls system operation. The system is provided with a video
interface 22, a display interface 24, a computer interface 26, and a
system interface 28. Interfaces 22, 24, and 26 serve to move data, under
computer control, into and out of a display buffer 30. Display buffer 30
is high-speed random-access memory of sufficient size to store video data
for a complete frame which is to be displayed in a scoreboard of the type
suitable for use in large stadia. As is well known in the television art,
a complete frame of video information is usually formed of two interlaced
fields of information displayed by scanning horizontally in a raster
fashion. For the purposes of this application, however, it will be
considered that a "frame" of video information is comprised of but one
field rather than two. Accordingly, a frame of video information is
comprised of n horizontal lines forming one field. Such a frame can be
obtained from a video source merely discarding the second field.
A statisfactory description of a typical stadium scoreboard is given in the
aforementioned U.S. Pat. No. 3,941,926, particularly FIGS. 5, 6, 13, 14,
9, 10, 11A and the associated descriptive portions of the patent. That
patent, including the aforementioned portions thereof, are hereby
incorporated by reference.
The system interface 28 interfaces the computer system 20 to the various
buses, including the input bus 32, the output bus 34, the function select
bus 36, and the control bus 38. It will be observed that each of the
interfaces 22, 24, and 26 is connected to these buses so that the computer
system 20 can operate the desired interface by sending appropriate signals
on the various bus lines through the system interface 28. It should also
be noted that this bus arrangement permits additional display interfaces
to be added to the system merely by tying them to the bus structure. Thus,
for example, additional display interfaces could be added for multiple
scoreboards, or other custom-designed devices could be added to the system
by the use of an appropriate interface design of the type detailed in this
specification.
The transmission of data between the various interfaces and the display
buffer 30 is similarly accomplished by the use of a bus structure,
including data bus 40, address bus 42, and control data bus 44. It will be
observed that the buffer 30 is connected to each of the display interfaces
via this bus structure.
The video interface 22 receives digitized video information from a video
converter and display control 46 which, in turn, is connected to a video
source 48. The video source may be the line feed from a network broadcast,
a video tape recorder or other source. Converter and display control 46
output also drives a monitor 50 so that the control room may preview what
is to be displayed.
The video interface 22 connects the video converter 46 to the display
buffer 30 via the buses 40, 42, and 44. The display interface 24 connects
the display buffer 30 to the scoreboard display which includes a matrix of
variable intensity display devices, such as light bulbs. The data is
utilized to illuminate these devices in order to reproduce the video
information for the benefit of spectators at a sporting event, concert, or
the like.
The computer interface 26 provides a similar data connection between the
computer and the display buffer 30. This interface is utilized for
providing pictorial or text input from the computer ststey as, for
example, from a disk storage device to the display buffer 30. An example
of this type of usage would be the display of statistics on individual
players during a baseball game, which statistics are stored in the
computer memory and updated as the game progresses. Other examples of the
use of the computer interface include displaying portraits of a player or
single or multiple frame cartoons which have been stored in the computer
system memory.
As indicated in the background portion of this specification, a principal
object of the invention is to remove the computer system from the direct
data path so as to obtain higher rates of data handling. It will be
observed that the interfaces 22 and 24, although under computer control,
directly receive and transmit data to and from the display buffer without
utilizing the computer's memory capabilities or its data break facility.
Computer interface 26 does employ the computer's memory facility but only
for the special purposes indicated where higher data handling rates are
not necessary.
Computer System and System Interface
The computer system 20 may be any desired computer system capable of
operating under the conditions specified herein. Preferably it will be a
mini computer utilizing a common busing structure and having a data break
facility. Mini computers well suited for this purpose are manufactured by
the Digital Equipment Corporation. of Maynard, Mass.; and, in particular,
their series PDP8 and 11 are suitable for use in the present invention.
The system interface 28 may be custom designed for a given installation or
available hardware can be utilized. For example, the system interface 28
could be the Digital Equipment Corporation Model DR11B which is capable of
interfacing the buses 32, 34, 36, and 38 to the computer. The necessary
functions for the system interface are indicated in block form and will be
described for completeness. Upon command by an operator, the computer
system, via the system interface, will cause one of the selected
interfaces 22, 24, or 26 to be enabled to transfer data into or out of the
display bufer 30. A command is provided to the data register 52 while the
device selected is identified by a device code in the status register 54.
The code set in the status register selects one of three interfaces 22, 24
or 26. For the purpose of discussion, it will be assumed that the video
interface 22 has been specified in status register 54. Thus, the device
code placed in the status register will match the code assigned to
function decode register 56 of the video interface 22. When a "Go" is sent
by the system interface on the control bus 38, the timing control 58 of
the video interface initiates operation. If the function selected is a
transfer of data from the video converter 46 to the buffer 30, such a
transfer is initiated. The data register 60 receives the digitized data
from the video converter 46 and outputs it via the data bus 40 to the
display buffer 30. The address register 63 via the address bus 42
indicates the correct address for storing the data in the buffer.
Upon transferring data for a complete video frame, a signal is sent via
control bus 38 to advise the system interface 28 that the data transfer is
complete. Computer 20 will then change the code in the status register 54
to select a new device and change the command by changing the code in data
register 52. If, for example, it is desired to transmit the data stored in
the ram 30 to the display boards, the function code for the display
interface 24 would again be loaded into status register 54, while the data
register would contain the proper code for transmitting data to the board.
Alternatively, the system is capable of transferring data to and from the
computer system for specialized purposes. This transfer, as with every
other transfer of data in the present invention, is to and from the ram
30. For example, video from source 48 can be received through the video
interface and stored in the buffer 30; and then, through the computer
interface 26, sent to the computer system for storage on disk or other
storage devices. After appropriate processing or when desired, the
computer-stored information can be fed back through the computer interface
26 to the RAM and then transferred to the board or to the video monitor 50
for editing or previewing.
The operation of the video interface will be discussed in greater detail in
connection with FIG. 2. The display interface and computer interface are
substantially identical with regard to the hardware and the function
performed. They do differ, one from the other, in some respects in order
to accommodate the particular function to which they are dedicated. The
video interface 22 is provided with a command register 62 which selects
the particular operation which the interface performs. Similarly, the
display interface and the computer interface have command registers 64 and
66, respectively. All three interfaces similarly include a function
decoder to recognize when a given interface is selected. The video
interface includes data register 60 capable of transferring data to and
from the video converter 46 and to and from the data bus 40. The computer
interface includes a similar data register 68.
The display interface is provided with a data multiplexing register 70 for
receiving data from data bus 40 and transmitting it via the
parallel-to-serial converter 72 to the display boards. When it is desired
to transmit this information from the display buffer to the scoreboard the
display interface 24 is selected by the computer system. The display
interface is provided with addressing circuits including a module address
register 80, an address register counter 82, a read only memory (ROM) look
up table, an adder 86 and an address register 88. These elements function
to alter the sequence of data transmission from the display buffer to the
displays. In general, video data is uusally transmitted in a raster format
comprised of a large number of horizontal lines of data. The present
system stores the data in the buffer 30 in that format.
It is desirable in large displays of the present type to transmit the data
in a different format, namely, in modules so many elements high by so many
elements wide whereby the power requirements for the display board can be
evenly distributed. Thus, for example, a display board which is 60 lamps
high by 144 lamps wide, a typical module might be on the order of 20 lamps
high by 72 lamps wide and each module might, in turn, be further divided
into sub-modules of 10 by 12 lamps for utilizing a three phase power
supply. See the aforementioned U.S. Pat. No. 3,941,926, particularly FIGS.
5 and 6 and the associated description for a further discussion of this
aspect of the invention.
The addressing elements in the display interface perform the necessary
address mapping to convert data which has been stored in a raster fashion
to a module format for transmission to the scoreboard. Stored in the ROM
84 is the correct addressing sequence for extracting data from the display
buffer in modules. The module address register 80 keeps track of which
module is being addressed and its output is transmitted to the data
multiplexer 70 before each block of data is sent to the scoreboard. The
address register 82 and the ROM 84 cause the correct address to be loaded
into the address register 88 for obtaining the correct block of data from
the RAM 30 for transmission on data bus 40 to the data multiplexer 70.
Thus, the module address register 80 informs the board where each block of
data sent from the multiplexer is to be displayed while the address
register counter and ROM instruct the address register 88 where to obtain
the next module of data whitin the display buffer 30.
The display interface is provided with a clock 90, which is used throughout
the scoreboard display system. It is noted, however, that the computer
system 20 operates independently of the display clock 90.
The computer interface 26 is provided with a data multiplexing capability
in the form of register 92 for transmitting information from the data bus
40 to the computer input bus 32 when it is desired to store information in
the computer system. With the foregoing exception, the interfaces 22, 24
and 26 are essentially the same in that they interface with the computer
system through the system interface 28 and transmit to and receive data
from the display buffer 30. The video interface is described in greater
detail in connection with FIG. 2 and much of the description there applies
to the display and the computer interfaces.
Summarizing the structure thus far described, it will be apparent that a
busing structure is disclosed to which are connected: the video, display,
and computer interfaces. By means of this structure, it is possible to
transfer video data to or from any of the interfaces, using the display
buffer 30 as the intermediary. Thus, for example, it is possible to
transfer data from the computer system 20 to the video inerface or to the
display interface. This would be accomplished by outputting the data from
the computer system to the output bus 34, through the computer interface
26, and into the display buffer 30. The data would then be transferred
from the display buffer to either the display interface for transmissiom
to the scoreboard or the video interface for transmission to a monitor 50
via the data bus 40. The reverse data transfer is also possible wherein
the video interface provides data from the video converter 46 to the data
bus 40 and the display buffer 30. That data can then be provided to the
display interface 24 for transmission to the display board or, via the
computer interface 26 provided to the input bus 32 for receipt and
storage by the computer system 20. The versatility of the system according
to the invention is thus apparent and the extreme flexibility obtained is
a significant advantage of the invention over the prior art.
Video Interface
Referring now to FIG. 2, the video interface is illustrated in block
diagram form. The various buses by which the interface communicates with
the system are indicated. The function select bus 36 is connected to the
decoding register 56 so that when the transmitted code matches the code in
the register an output, VSEL, is produced which is applied to AND gates
100 and 110. Subsequently, when the go signal is received from the control
bus 38 gate 100 is enabled thereby providing a signal to the command
register 62 to read the contents of the output bus 34 to determine what
operation is desired. The output bus comprises four lines which are
applied to the indicated inputs of the command register. Depending upon
the code transmitted on the output bus, the command register is instructed
to operate in one of several modes. Inputs are also provided for various
display options which will be described subsequently.
The sync loss input to the command register 62 is an indication that some
time during the receipt of video data synchronization was lost and that
the picture information is faulty. Upon receipt of this signal the command
register notifies the computer system via the input bus 32. The DIS/REC
input to the command register determines whether the command register
operates in the record or display mode. The display mode transmits
digitized video information from the display buffer 30 to the video
converter 46 for display on monitor 50. The display mode is utilized for
previewing or for testing the system. The record mode transfers data from
the video converter to the display buffer 30.
The ready and run inputs to the command register, drive panel lights 120
and 122 to provide the operator with information as to the status of the
system. The ready light indicates that the system is waiting for
instructions from the operator to begin processing while the run light
indicates that viewo is being processed by the system. The mode input,
depending upon the state of the switch 124, instructs the command register
to blank an unused portion of the display board so that ransom data is not
displayed adjacent a meaningful display.
It will be recalled that the go signal initiates operation of the command
register to read the data on the output bus 34. As a result latches 126
and 128 are toggled depending upon the mode selected. In the case of
flipflop 126 the output is high when the record mode is selected. Flipflop
128 produces an output, VRUN, when the go signal is received in the
command register. Both flipflops are clocked by the vertical sync signal
and their outputs are provided to the timing and control circuit 58
discussed in connection with FIG. 3. Also provided to the timing and
control circuit is the VCLK signal generated by the video converter of
FIGS. 9A and B.
Depending upon which mode (Record or Display) the command register is
operating in, AND gate 110 or 130 will generate a signal via OR gate 132
producing an output on the control bus 38 to the computer after a complete
frame of video data has been transferred. The inputs to AND gate 130 are
the VRUN signal and the bottom signal generated by the video converter
indicating the last line of the frame.
The timing and control circuit 58, described in greater detail in
connection with FIG. 3, operates the double buffered data register 60 for
inputting or outputting data to or from the data bus 40 and for correctly
addressing this data via address register 63 and the address bus 42. Data
register 60 is a double buffered register arrangement employing registers
134 and 136. Each register is capable of serial and parallel transfer of
data. The double buffer control bus 138 operates the buffers in a known
manner wherein one of the registers loads data while the other transmits
or receives data. This provides an extremely fast data transfer mechanism
and, in particular, since the transfer to the data bus 40 is parallel the
display buffer 30 may be quickly loaded with the video data for a full
frame. Tri-state gates 135, 137, 139 and 141 control the data flow to and
from the registers 134 and 136. Thus, during serial transfer of data from
the converter to the display buffer, gates 139 and 141 present a high
impedance to permit serial loading of registers 134 and 136.
Timing and Control Circuit
Referring now to FIG. 3, a schematic of the timing and control circuit is
illustrated. This circuit, depending upon whether the video interface is
in the record or display mode, causes the proper loading and transmission
of data through the buffers 60. A counter 150 is clocked from an AND gate
152 which has as its input the VRUN signal and the VCLK signal. VRUN is a
signal generated from the video interface which starts the video data
moving to or from the video interface. The VLCK signal is generated by the
video converter circuit and is described in connection therewith. Counter
150 counts to 12 and produces outputs on lines 154 and 156. A "count one"
signal is produced on line 154 and applied to OR gate 158. The output on
line 156 is the "count 12" pulse and is applied to OR gate 160 and AND
gate 162. The other input to gate 160 is from AND gate 164 which, in turn,
has as its inputs the Read signal produced by gate 166 and the Add Z
signal from the Q output of flipflop 168. OR gate 160 drives flipflop 170
which controls the double buffered operation of the register 60 so as to
alternate loading and transmission of data to and from the registers 134
and 136 (FIG. 2).
Gate 162 also receives Rec signal and its output is provided to OR gate 172
which, in turn, is provided to a pair of one shots 174 and 176 connected
in series. The other input to gate 172 is from gate 178 whose inputs are
the display signal and the output of gate 158. The output of the one shot
176 is provided as an input to AND gates 180 and 166 and as the clock
input to the flipflop 168.
For a purpose to be described, the flipflop 168 has its present input
connected to the output of an OR gate 182, the inputs of which are the top
signa and the output of gate 184, the inputs to the latter being the
horizontal sync and the vertical enable signals. The operation of the
circuit as thus far described is relatively straightforward. The counter
150 drives the flipflop 170 to alternate loading and transmission of data
to and from the data registers 134 and 136. Thus, when the Q output is
high, the left register will load data while the right register will
transmit or receive data. The count one and count twelve outputs from the
counter 150 also control generation of the read and write logic gates 180
and 166. It will be recalled that in the Display mode data is loaded in
parallel from the display buffer and transmitted in serial fashion to the
monitor for previewing, etc. In the Record mode data is received from the
video source in series and provided to the display buffer in parallel.
Thus, in the Display mode gates 178 and 166 are enabled by the Display
signal producing the read signal from gate 166 and operating the flipflop
168. Conversely, in the Record mode gates 162 and 180 are enabled
producing the write enable signal applied to the control data bus 44.
When operating in the display mode, an important feature of the timing and
control circuit is the recognition of the start of a line and particularly
the first line in a frame. It is necessary at the beginning of each line
to preload one of the registers so that data is present therein for the
first cycle of transmission. This is accomplished by flipflop 168 and the
gates associated therewith. At the beginning of every frame the top signal
goes high presetting flipflop 168 via the gate 182. This enables the Q
output designated Add Z which is anded when the Read signal from gate 166
to toggle the flipflop 170. Thus, at the beginning of every frame the
first data work to be transmitted is preloaded into the buffers prior to
the first clock cyle. After the preload, flipflop 168 is reset by the
output from one shot delay 176 applied to the clock input. After the first
line the add Z signal is produced under control of gate 184 in response to
the horizontal sync and vertical enable signals which are the inputs to
that gate. Thus, flipflop 170 changes state when any one of the following
three conditions occur: (1) just after the first read cycle following a
"top" signal when in the display mode; (2) just after the read cycle
produced following the "HSYNC" on every line except the top line of a
frame, when in the display mode; (3) on every count 12, which counter 150
produces, in both the display or record mode.
Referring now to the top portion of FIG. 3, the gating for the registers
134 and 136 is illustrated. The dashed line separates the gating for each
of the data registers. The gating for each register is identical. The
gating for the left data register 134 generates four outputs on lines 183,
185, 187 and 189. The output on line 183 is the serial control operating
the control line for the tri-state gates 139 (FIG. 2) which selectively
connect or disconnect the serial output from data register 134 to the
video converter 46. This output is produced by NAND gate 186 which
receives as its input the output from flipflop 170 and the Display signal.
Thus, when the left register 134 is selected and the Display mode is
chosen, an output is produced to permit serial data transfers to the video
converter 46.
Line 185 is the control line which either enables or disenables the
parallel outputs of the data register associated with it. It controls the
operation of the tri-state gates internal to the gates internal to the
data register 134.
Line 187 is the mode select line enabling the register to either be loaded
in parallel or shift data in or out in serial. Line 189 is the clock
signal. In the display mode the clock signal provides the read pulse from
gate 166 to parallel load one of the registers and the VCLK signals to
serially shift the data out. In the record mode the clock line 189 applies
VCLK signals only (since the write pulse from gate 180 is applied to the
display buffer 30).
Summarizing the operation of the FIG. 3 circuit, in response to certain
inputs, including the VCLK, VRUN, HSYNC and VENA signals, the circuit
causes the two data registers 134 and 136 to alternate between loading and
transmission of data to or from the display buffer. The loading and
transmission is in a double buffer format to maintain maximum data
handling rates. Provision is made for preloading one of the data registers
prior to the beginning of each line.
Display format: Standard Zoom and Wide Screen
Referring now to FIG. 4, there is illustrated a representation of a frame
of video information. As is well known in the television art, a complete
frame of video information is formed of two interlaced fields of
information displayed by scanning horizontally in a raster fashion. For
the present purposes it will be considered that a frame of video
information is comprised of but one field rather than two. Accordingly, a
frame of video information 250 is comprised of n horizontal lines
comprising one field. Such a frame can be obtained from any video source
merely by discarding the second field.
Frame 250 illustrates a video display test pattern over a substantial
portion of the frame. The dashed line 252 illusrates that portion of the
video frame which is utilized during a standard operating mode of the
display system. In the standard operating mode substantially all of the
frame is utilized with the omission of only the edges of the frame. Thus,
as illustrated in FIG. 5, when operating in the standard mode the entire
test pattern is illustrated with the correct aspect ratio of height to
width. In the standard operating mode, as will be described in connection
with the video converter and display control circuitry, the horizontal
sampling rate is one-half that of the master clock, MCLK, while the
vertical circuitry utilizes every other horizontal line of data in the
frame.
A second mode of operation, conveniently referred to as the zoom mode,
displays a portion of the video frame indicated by the dotted box 254. In
the zoom mode a selected portion of the video frame is displayed over the
entire display board. In this manner an "enlargement" of the selected
portion is achieved while maintaining the proper aspect ratio. This
enlargement is achieved by utilizing every line of the field rather than
every other line while at the same time doubling the horizontal sampling
rate to equal MCLK. This prevents loss of resolution. The zoom display
finds use for displaying close plays in a sporting event or other fine
detail as may be desired. The result of utilizing the zoom mode is
illustrated in FIG. 6.
A third display mode is possible with the present invention and will be
hereafter referred to as the wide screen mode. In this mode, in a manner
similar to the zoom mode, every line of the field is utilized. Again, as
with the zoom mode, the horizontal sampling rate is double that of the
standard mode. The horizontal length displayed by the wide screen mode,
however, is the same as the standard mode as indicated by the dashed box
256. The wide screen mode finds particular application to certain types of
sporting events as, for example, at racetracks where it is desired to show
the entire field of horses in a given race. Under these circumstances, to
utilize all the video data available an elongated display board is
employed. The use of every line in the field maintains the proper aspect
ratio between vertical and horizontal components of the image when the
fast clock rate is employed.
For practical reasons it is not desirable nor economically feasible to
increase the height of the display board in proportion to the increased
width. In the wide screen format this problem is resolved by nevertheless
utilizing every line in t | | |
