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BACKGROUND OF THE INVENTION
This invention relates to a signal-transmission system, and more
particularly to a signal-transmission system capable of controlling errors
for error-free transmission of static image signals.
Transmission of a static image by means of a telephone line system is
expected to be realized in the near future because the existing telephone
facilities are readily available for use. Particularly where transmission
of a static image is undertaken through the telephone line system, there
is the advantage of allowing said transmission to be carried out between
any given localities only when so desired. For transmission of a static
image of good picture quality through the telephone line system, however,
it is necessary to apply digital transmission, shorten the time of
transmission by using bit-reduction technique and applying high speed
MODEM, and further suppress occurrence of errors resulting from the
required high speed transmission of data signals with bit-reduction
technique.
A static image transmission system includes a facsimile transmission
system. This system carries out transmission of static images representing
documents or bills between the transmitter and receiver through a
transmission line. Application of, for example, a telephone line system
for transmission of data signals of narrow frequency band enables the
transmission area of an image to be more freely chosen over a broader
range then when a private line is used for such transmission. However,
application of the telephone line system has the drawback that random or
burst errors are likely to arise in transmitted data due to appearance of
noises on the transmission line or intrusion of noises thereinto from an
external source. Known literature on such transmission errors and control
thereof includes "Errors and error control" by H. O. Burton and D. D.
Sullivan Proc. IEEE, vol. 60, No. 11, November, 1972. Further, an
automatic repeat request (ARQ) system is already known as a signal
transmission system capable of controlling errors. This ARQ system is set
forth in "ARQ Error Control on the Satellite Channel" by A. G. Gatfield,
IEEE International Communications Conf., 1974, pp. 22B-1 to 22B-5. This
literature describes three types of the ARQ system, that is, "Stop and
Wait ARQ", "Continuous ARQ" and "Selective Repeat ARQ" and the respective
transmission efficiencies. It will be seen from this literature that the
"Selective Repeat ARQ" system has the highest transmission efficiency.
This "Selective Repeat ARQ" system is detailed in "A Selective Repeat ARQ
System" by A. G. Gatfield and T. R. Dobyns, COMSAT Laboratories, IEEE,
1974 NTC, pp. 189 to 195. However, application of the "Selective Repeat
ARQ" error control system for transmission of a static image would make it
necessary not only to install a memory device having a sufficiently large
capacity to handle an amount of data being transmitted between the
transmitter and receiver, but also additionally to provide means for
replacing (that is edit function means) previously supplied erroneous data
by fresh error-free data. For this reason, the "Selective Repeat ARQ"
error control system presents considerable difficulties in being applied
for facsimile transmission of data through a telephone line system and
consequently has not yet been put to practical use.
Where, with the "Selective Repeat ARQ" system, data transmission is
controlled by dividing a transmission line into two different channels,
that is, where a forward channel is used for data transmission, and a
backward channel is used for data error control, then a data block is
first sent forth through the forward channel from the transmitter to the
receiver. In this case, the receiver issues an acknowledgement (ACK)
control signal if data received is correct, and a negative acknowledgement
(NAK) control signal if data received is erroneous, both through the
backward channel. Where an error arises in either of the aforesaid control
signals (ACK and NAK) during transit through the backward channel, then
the transmitter supplies the receiver through the forward channel with an
enquiry (ENQ) signal demanding retransmission of a control signal. At this
time, the receiver again sends forth the control signal to the transmitter
through the backward channel. Where the transmitter receives the
retransmitted control signal in an error-free state, then the transmitter
undertakes the succeeding data transmission, if the control signal is of
the ACK type. If the control data is of the NAK type, then the transmitter
supplies the receiver with a fresh error-free data block corresponding to
the previously transmitted erroneous data block. Therefore, a check bit
such as an error detection bit or error correction bit must be attached to
an error control signal issued from the receiver to the transmitter
through the backward channel. This eventually increases a total
transmitted amount of control signals, causing completion of transmission
of correct data to consume a great deal of time with the resultant decline
in transmission efficiency.
SUMMARY OF THE INVENTION
The primary object of this invention is to provide a signal transmission
system which eliminates occurrence of errors during transit of a data
signal, thereby providing an image of good picture quality.
Another object of the invention is to provide a signal transmission system
which enables data signals to be transmitted with a higher efficiency than
has been possible in the past.
According to an aspect of the invention, there is provided a signal
transmission system capable of controlling errors which comprises a
transmission section including first memory means for storing data being
transmitted in the form having the prescribed block length measured by a
number of bits, control means for selecting a data block having the
prescribed serial number from among those which are stored in the memory
means, and means for attaching the prescribed check code to the selected
data block; and a receiving section including receiving means for
receiving a data block sent forth from the transmission section, detection
means for detecting an error in a data block received by the receiving
means, second memory means for successively storing only error-free
correct data blocks included in the received data blocks, and means for
issuing an error control signal indicating a demand for transmission of a
fresh error-free data block corresponding to the previously transmitted
data block whose error was detected by the detection means, and wherein
the transmission section transmits a fresh error-free data block
corresponding to an error control signal received from the receiving
section, without the necessity of determining whether the control signal
thus received erroneous or not.
The signal transmission system of this invention not only transmits a
static image of a good picture quality by means of the "Select Repeat ARQ"
system but also controls transmission of erroneous data without the
necessitive of attaching an error detection check bit to a control signal
transmitted by the receiving section through the backward channel.
Other features and advantages of this invention will be apparent from the
following description when taken in connection with the appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block circuit diagram of a signal transmission system
according to one embodiment of this invention;
FIG. 2 is a time chart illustrating the block-synchronizing operation
undertaken at commencement of data transmission by the signal transmission
system of the invention;
FIG. 3 indicates a detailed circuit arrangement of the transmission section
T.sub.t of the transmission side (forward transmission section) shown in
FIG. 1;
FIG. 4 is a time chart illustrating the operation of the circuit
arrangement of FIG. 3;
FIG. 5 shows a detailed circuit arrangement of the receiving side (formed
of the forward receiving section R.sub.r and backward transmission section
R.sub.t) shown in FIG. 1;
FIG. 6 is a time chart illustrating the operation of the circuit
arrangement of FIG. 5;
FIG. 7 presents a detailed circuit arrangement of the receiving section
T.sub.r of the transmission side (backward receiving section);
FIG. 8 is a time chart illustrating the operation of the circuit
arrangement of FIG. 7;
FIG. 9 is a detailed block circuit diagram associated with frequency
division undertaken by the separation circuit of FIG. 1;
FIG. 10 is a detailed block circuit diagram associated with time division
carried out by the separation circuit of FIG. 1;
FIG. 11 is a time chart illustrating the operation of the signal
transmission system of FIG. 1;
FIG. 12 is a curve diagram indicating the signal transmission efficiency of
the signal transmission system of this invention;
FIG. 13 is a time chart illustrating transmission of a pattern control
signal carried out by a signal transmission system according to another
embodiment of the invention;
FIG. 14 shows the arrangement of that circuit included in the forward
transmission section T.sub.r of FIG. 3 which has been modified for
transmission of the pattern control signal undertaken by a signal
transmission system according to said another embodiment;
FIG. 15 presents the arrangement of that circuit included in the receiving
side of FIG. 5 which has been modified for transmission of the pattern
control signal effected by said another embodiment; and
FIG. 16 indicates the arrangement of that circuit included in the backward
receiving section T.sub.r of FIG. 7 which has been modified for
transmission of the pattern control signal performed by said another
embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block circuit diagram of a signal transmission system according
to one embodiment of this invention. There will now be described the
transmission section (forward transmission section) T.sub.t and receiving
section (backward receiving section) T.sub.r of the transmission side. A
data source 11 is that of, for example, image signals being transmitted. A
data block-forming circuit 12 divides data signals delivered from the data
source 11 into data blocks each having a prescribed bit length formed of,
for example, 512 bits. This data block-forming circuit 12 divides signals
representing an image impressed on a single sheet of manuscript into, for
example, fifteen data blocks. A memory circuit 13 is a random access
memory (RAM) for successively storing data blocks. A check code-attaching
circuit 14 attaches an error detection check code (CRCC) of, for example,
sixteen bits to a data block read out of the memory circuit 13.
A forward MODEM15 modulates a data block signal sent forth from the check
code-attaching circuit 14. A separation circuit 16 carries out the time
division or frequency division of the modulated data block signal. An
output signal from the separation circuit 16 is transmitted to the
receiving side through a common transmission channel 17 (in this case
acting as a forward channel).
The separation circuit 16 carries out the later described frequency
division or time division of a control signal (ACK or NAK signal) supplied
from the receiving side through the common transmission channel 17 (now
acting as a backward channel). A backward MODEM18 demodulates the control
signal (ACK or NAK) issued from the separation circuit 16. The "Selective
Repeat ARQ" system first transmits all data blocks, regardless of whether
errors may or may not arise during transmission of the data blocks and
then supplies only a fresh error-free data block corresponding to that
which presented an error during transmission.
When acting as a backward channel for transmitting the serial number of a
data block in which an error occurred during transmission, the common
transmission channel 17 may be permanently designed for time division or
frequency division. With the signal transmission system of this invention,
the transmission side makes no response to an ACK control signal received
from the receiving side through the backward channel, whether the
transmission channel 17 is designed for time division or frequency
division, and supplies the receiving side only with a fresh error-free
data block corresponding to the serial data block number represented by a
NAK control signal sent forth from the receiving side.
An error control circuit 19 is supplied with a control signal delivered
from the backward MODEM18. Where the transmission side makes no response
to the control signal (that is, an ACK signal), then the error control
circuit 19 allows the succeeding data block to be transmitted to the
receiving side. Where the control signal denotes a serial data block
number, then the error control circuit 19 causes a fresh error-free data
block corresponding to said data block number to be delivered to the
receiving side. Namely, the error control circuit 19 specifies a data
block to be read next time out of the memory circuit 13.
There will now be described the receiving section (forward receiving
section) R.sub.r and transmitting section (backward transmitting section)
R.sub.t of the receiving side. A separation circuit 20 has the same
arrangement and function as the first-mentioned separation circuit 16. As
later described, the receiver's separation circuit 20 may be designed for
time division or frequency division. A forward MODEM21 demodulates a data
block supplied from the transmission side through the common transmission
channel 17 acting as a forward channel and separation circuit 20. An error
detection circuit 22 determines whether a data block sent forth from the
transmission side has an error.
A receiver's memory circuit 23 is of the RAM type like the transmitter's
memory circuit 13. The memory circuit 23 is stored with a data block which
has been determined to be error-free by the error detection circuit 22. A
display device 24 is a terminal device of the subject signal transmission
system for indicating data blocks stored in the memory circuit 23 in the
form of characters or pictorial patterns.
A data block issued from the transmission side whose error has been
detected by the error detection circuit 22 is not stored in the memory
circuit 23. An error control signal generator 25 produces an
acknowledgement control signal (ACK) when a data block delivered from the
transmission side to the receiving side proves error-free, and a negative
acknowledgement control signal (NAK) and the serial number of said
erroneous data block, when the data block thus received is found
erroneous. A backward MODEM26 demodulates a control signal supplied from
the error control signal generator 25. The control signal (ACK or NAK) is
sent from the receiving side to the transmission side through the
separation circuit 20 and the common transmission channel 17 now acting as
a backward channel in turn.
The signal transmission system of this invention is adapted for still
picture transmission of static data. Based on the generally estimated
maximum number of manuscript sheets, being transmitted during one
transmission cycle static data handled by a still picture transmission
system generally has as large an amount as about one million bits. In this
case, establishment of a data block-synchronizing method before
commencement of transfer of data blocks between the transmitter and
receiver, followed by transmission of data blocks each having a prescribed
bit number attains a higher transmission efficiency than the process of
undertaking synchronization, each time a data block is transmitted.
Obviously, bit synchronization is already established, starting with
commencement of transmission when a telephone line system between the
transmitter and receiver is set for transmission of data blocks. As seen
from the time chart of FIG. 2, therefore, the signal transmission system
of this invention is so designed that data block synchronization is
established between the transmitter and receiver before data blocks are
transmitted. The transmission section T.sub.t of the transmission side
sends forth a data block synchronization code SYN and plurality of dummy
data blocks DB's shown in FIG. 2(a) to the receiving side through the
transmission channel as illustrated in FIG. 2(b). When the receiving
section R.sub.r of the receiving side detects the data block
synchronization code SYN, then the transmitting section R.sub.t of the
receiving side issues, as indicated in FIG. 2(c), an ACK control signal to
the transmission side through a backward channel, if a data block received
is found error-free. When the receiving section T.sub.r of the
transmission side detects said ACK control signal as shown in FIG. 2(d),
then the transmission side issues data blocks DATA1 to DATAn is succession
to the receiving side, starting with the end of the prescribed period of
time T.sub.o after issue of the data block synchronization code SYN. When
not detecting the data block synchronization code SYN, the receiving side
gives no response to the transmission side. In this case, the transmission
section T.sub.t of the transmission side again issues a data block
synchronization code SYN to the receiving side at the end of the
prescribed period of time T.sub.o, thereby establishing transmission
synchronization between both sides. Description is not given of a control
circuit for establishing the data block synchronization, because said
control circuit is not related to the object of this invention.
FIG. 3 shows the detailed circuit arrangement of the formed transmission
section T.sub.t of the signal transmission system of FIG. 1. There will
now be described by reference to the time chart of FIG. 4 the operation of
the circuit arrangement of FIG. 3. Now let it be assumed that referential
clock pulses CP (FIG. 4(a)) are issued from the control circuit (not
shown) of the subject signal transmission system. The referential clock
pulse CP is conducted to a register 31 and an 8-bit counter 32 through an
AND gate 30. In this case, data block synchronization should be
established, as previously mentioned, before data blocks are delivered
from the transmission side to the receiving side. To this end, the control
circuit issues a read-in pulse (FIG. 4(b)) to the register 31. The
prescribed data block synchronization code SYN stored in the register 31
is chosen to be formed of, for example, eight bits as 01111110. An input
set pulse or restart pulse (FIG. 4(e)) issued from the control circuit
sets a flip-flop circuit 34, as shown in FIG. 4(f)), through an OR circuit
33. An output signal from the set output terminal Q of the flip-flop
circuit 34 which has a logic level of "1" is conducted to AND gates 30,
35. Therefore, the register 31 is supplied, as shown in FIG. 4(c), with
the bits of the prescribed data block synchronization code SYN in
succession, starting with the point of time at which said register 31
receives a read-in pulse.
The data block synchronization code SYN is stored in a buffer memory 37
through the AND gate 35 and OR gate 36, and further delivered to the
receiving side after modulated by the forward MODEM15. A counter 32 issues
one block count pulse, each time the counter 32 counts the same number of
clock pulses as the eight bits constituting the data block synchronization
code SYN, thereby resetting the flip-flop circuit 34 as shown in FIG.
4(f). Since, at this time, an output signal from the set output terminal Q
of the flip-flop circuit 34 has a logic level of "0", transmission of the
data block synchronization code SYN stops. Therefore, the signal
transmission system commences transmission of data blocks.
At the same time as the above-mentioned operation, clock pulses are also
counted by an N-bit counter 39 through an AND gate 38. This N-bit counter
39 sends forth block count pulses (FIG. 4(h)) each denoting one data block
formed of an N number of bits, for example, 512 bits. With the foregoing
embodiment, the whole data impressed on a single sheet of manuscript is
transmitted in the form divided into fifteen data blocks as shown in FIG.
4(j). A counter 40 for counting the number of a specified memory address
in which a data block is to be written (hereinafter simply referred to as
"a write block address counter") specifies the numbers of the memory
addresses which correspond to the serial numbers of the respective data
blocks upon receipt of a block count pulse from the N-bit counter 39. A
digital multiplexer (abbreviated as "DMPX2") 41 generates output signals
OUT1 to OUT15 corresponding to the serial numbers of data blocks as shown
in FIG. 4(i). The output signals are supplied to the gate circuits (G1)
42-44 and memories (MEMORY1 to MEMORY15) 45-47, all corresponding to the
serial numbers of the data blocks. Where each of the memories 45-47 has
its enable terminal supplied with a data signal having a logic level of
"1", then the memory is rendered ready to store the data signal. Where a
data signal having a logic level of 37 0" is brought to the enable
terminal, then the memory is prevented from storing the data signal. Thus,
the original data of a manuscript being sent forth from the transmitter to
the receiver is conducted in the form of data blocks through the gate
circuits (G1) 42-44 to the memories (MEMORY1 to MEMORY15) 45-47
corresponding to the specified serial numbers of data blocks. The
respective memories (MEMORY1 to MEMORY15) are stored with essential data
blocks each having an N number of (for example, 512) bits. TCM registers
(TCM1 to TCM15) 48-50 provided to correspond to the respective memories
(MEMORY1 to MEMORY15) 45-47 are stored with the serial numbers of
erroneous data blocks. If the data blocks are found error-free, then the
TCM registers 48-50 are cleared of the contents by a clear pulse CLR.
However, in the initial condition of the subject signal transmission
system, where transmission of data is commenced, the TCM registers 48-50
are stored with the serial numbers of all data blocks on the assumption
that said data blocks are erroneous. The TCM registers 48-50 have the
contents successively emptied by a clear signal issued from a switch
circuit actuated by the later described signal "A", according as the data
blocks are transmitted one after another. It will be noted that the gate
circuits 42-44, memories 45-47 and TCM registers 48-50 respectively have
the same function and provided in a number of fifteen to correspond to the
fifteen output terminals OUT1-OUT15 of the digital multiplexer
(abbreviated as "DMPX1") 41.
Where the forward and backward channels are designed for frequency
division, then the receiving side sends back the serial number of an
erroneous data block to the transmission side together with an NAK control
signal through the backward channel. At this time, the contents of TCM
registers (TCM1 to TCM15) 48-50 are changed through the process
illustrated in FIG. 4, causing an error control signal specifying the
serial number of an erroneous data block to be written in the
corresponding unit of the TCM registers (TCM1 to TCM15) 48 to 50. The
serial numbers of erroneous data blocks stored in parallel in the TCM
registers (TCM1 to TCM15) 48 to 50 are conducted to a switch 52, where the
transmission of said serial numbers are controlled by an output signal "A"
from an OR circuit 53. The OR circuit 53 is already supplied with a data
start pulse, end pulse and skip pulse. The data start pulse is the one
issued from the control circuit at the end of the prescribed period of
time T.sub.o after data block synchronization is established between the
transmission side and receiving side. This data start pulse instructs
commencement of data block transmission, as shown in FIG. 4(k). The end
pulse is issued, as shown in FIG. 4(n), after one data block is
transmitted in the form provided with a serial block number and a check
code CRCC. The skip pulse is produced, as shown in FIG. 4(l), when a
control operation is undertaken regarding the transmission of a fresh
error-free data block corresponding to the previously transmitted
erroneous data block, and has a function of omitting the retransmission of
the succeeding error-free data blocks already supplied to the receiver in
order to effect the smooth continuous transmission of data blocks in the
serial order.
As previously described, with the "Selective Repeat ARQ" system, all data
blocks D1 to D15 are first transmitted to the receiving side, and next
fresh error-free data blocks corresponding to the data blocks in which an
error occurred during the first step transmission are supplied to the
receiving side. To this end, the OR circuit 54 examines the contents of
the TCM registers (TCM1 to TCM15) 48-50 which are brought to said OR
circuit 54 through the switch circuit 52. If the OR circuit 54 issues an
output signal having a logic level of "1" as the result of said
examination, then if means that it is necessary to transmit a fresh
error-free data block corresponding to the contents (the serial number of
an erroneous data block) of any of the TCM registers (TCM1 to TCM15) 48-50
in which at least one of the four bits constituting said serial number has
a logic level of "1". If the OR circuit 54 issues an output signal having
a logic level of "0", then it means that a data block represented by said
serial data block number has already been transmitted to the receiver in
an error-free state, making it necessary to retransmit said data block.
Where, therefore, an output from the OR circuit 54 has a logic level of
"0", then an inverter 55 sends forth a skip pulse (FIG. 4(l)), causing
transmission to be shifted to the immediately following data block. Where
the OR circuit 54 issues an output signal having a logic level of "1", the
serial number of the data block delivered from the switch circuit 52 is
conducted to a multiplexer 60 through one or more of AND circuits 56-59.
The multiplexer 60 causes a data block corresponding to the specified
serial number to be read out of the selected one of the memories MEMORY1
to MEMORY15 as shown in FIG. 4(m).
A data block number register 61 generates the serial number a data block
being transmitted. A data block delivered from the multiplexer 60 is
delayed by four bits constituting its serial number by a data block delay
circuit 62, causing the serial number to be attached to the forward side
of the data block. A check bit code CRCC is attached by a check code
generator 64 to an assembly of the data block and its serial number which
have passed through an OR circuit 63. Therefore, an OR circuit 65 produces
a fully assembled data block signal shown in FIG. 4(n) which is formed of
the data block, its serial number and check bit code CRCC. This data block
signal is stored in a buffer memory BM37 through an AND circuit 66 and OR
circuit 36. An end pulse is produced as shown in FIG. 4(o), each time one
data block signal is fully assembled. At the issue of said end pulse,
preparatory operations are carried out for formation of the succeeding
data block signal. A data block signal (FIG. 4(n)) stored in the buffer
memory BM37 (FIG. 4(p)) is read out at the prescribed speed, and sent
forth to the transmission channel through the forward MODEM15 and
separation circuit 16.
FIG. 5 shows the detailed circuit arrangement of the forward receiving
section R.sub.r and backward transmission section R.sub.t of the signal
transmission system of FIG. 1. There will now be described the operation
of said circuit arrangement by reference to the time chart of FIG. 6. A
data block is transmitted from the transmission side to the receiving side
through the forward channel. A data block signal (FIG. 6(b)) formed of a
serial number, data block and check bit code is modulated by a forward
MODEM21 and stored in a buffer memory BM70, and then conducted to a
register 71 by clock pulses (FIG. 6(a)). However, data block
synchronization should be established before the signal transmission
system is loaded with a data block signal. To this end, the contents of
the register 71 is compared by a comparator 72 with a data block
synchronization code SYN formed of eight bits as "01111110". Where both
bit arrangements coincide as the result of comparison, then the comparator
72 issues a set pulse. This set pulse sets a flip-flop circuit (FF2) 73 as
shown in FIG. 6(c), causing a flip-flop circuit (FF3) 75 to be reset
through an OR circuit 74. Where an output from the set output terminal Q
of the flip-flop circuit (FF2) 73 is supplied to a register 77 through an
AND circuit 76, then the aforesaid read-in pulse is stored in said
register 77. Accordingly, an acknowledgement (ACK) signal (FIG. 6(p))
formed of 4 bits as "0110" is modulated by a backward MODEM26 through an
OR circuit 78, and buffer memory 79 and then carried to the transmitter.
An N data block counter 81 generates one count pulse, each time the
counter 81 counts an N number of data blocks by data block count pulses
conducted through an AND circuit 80 after detection of the data block
synchronization code SYN. An output count pulse from the N data block
counter 81 sets the flip-flop circuit (FF3) 75 as shown in FIG. 6(d). The
aforesaid N number of data blocks immediately following the data block
synchronization code SYN are dummy data blocks as seen from the time chart
of FIG. 2. After these dummy data blocks are counted, substantial data
blocks are stored in the memory device. While said N number of dummy data
blocks are received, it is unnecessary to undertake error control. The
value of N is determined according to, for example, the forward
transmission speed, the bit number of each data block and the channel
transmission time.
Where the data block synchronization code SYN is not detected in a train of
bits immediately following the dummy data blocks, then data restored in
the register 71 through the buffer memory 70 is supplied to a register 84
through an AND circuit 83. Where a serial block number is put, as shown in
FIG. 4(p), in the reader section of a data block signal, then the an
assembly of the data block and check code are read out in bit serial, as
shown in FIG. 6(e), from a register 84. The serial block number of the
data block read out in bit parallel of the register 84 is conducted to a
digital multiplexer (DMPX2) 85. As the result, that of the output
terminals OUT1 to OUT15 of the digital multiplexer (DMPX2) 85 which
corresponds to an input data block number issues a pulse (FIG. 6(f)) only
during the time width of the assembly of the data block and check code
represented by said data block number. The aforesaid assembly of a data
block and check code is supplied to an error detection code (CRCC) decoder
85 to be subjected to an error check. If the data block has an error, then
the ER terminal of the decoder 86 generates an error pulse (FIG. 6(g)). On
the other hand, an error-free data block which has passed through the
decoder 86 is stored in any of the memories (MEMORY1 to MEMORY15) 90-92
through the corresponding one of the AND circuits 87 to 89 which are
supplied with output signals (OUT1 to OUT15) corresponding to the
respective data blocks from the digital multiplexer (DMPX2) 85.
Now let it be assumed that an error is detected in data blocks D2.sub.e,
D4.sub.e as shown in FIG. 6(b). Then an error pulse (FIG. 6(g)) is issued
at the end of the erroneous data blocks D2.sub.e, D4.sub.e respectively.
Therefore, these erroneous data blocks D2.sub.e, D4.sub.e are not stored
in the corresponding memories MEMORY2, MEMORY4 as shown in FIGS. 6(i) and
6(k). On the other hand, error-free data blocks D1, D3 are stored in the
corresponding memories MEMORY1, MEMORY3. Namely, an erroneous data block
is prevented from being stored in a memory by the enable circuit thereof
which is supplied with an error pulse. The serial number of the erroneous
data block has to be stored in a memory to meet the subsequent receiver's
demand for the transmission side to send forth a fresh error-free data
block corresponding to said erroneous data block. Therefore, the serial
numbers of erroneous data blocks read out of the register 84 are delivered
to AND cireuits 95-98 through a delay circuit 94 to the written in the
corresponding erroneous data block number registers (RCM1 to RCM15) 99-101
upon receipt of an error pulse from the error detection code (CRCC)
decoder 86. This writing operation is undertaken while the output
terminals OUT1 to OUT15 of the digital multiplexer (DMPX2) 85 are
connected to the enable terminals of the corresponding erroneous data
block number registers (RCM1 to RCM15) 99-101 through inverters 102-104
and a delay circuit 105. Since the data blocks D1, D3 are error-free as
previously described, code bits constituting the serial block numbers of
these error-free data blocks D1, D3 are stored in the registers (RCM1 to
RCM15) 99-101 in the form of "0000" as illustrated in FIGS. 6(l) and 6(n).
Since the data blocks D2.sub.e, D4.sub.e are erroneous, code bits
constituting the serial numbers of those erroneous data blocks D2.sub.e,
D4.sub.e are stored in the registers RCM2, RCM4 in the form of "0010" and
"0100" respectively as indicated in FIGS. 6(m) and 6(o). Code bits
initially stored in the registers (RCM1 to RCM15) 99-101 are all set in
the form of "0000".
Output signals from the memories (MEMORY1 to MEMORY15) 90-92 are delivered
to a multiplexer (MPX2) 106. At this time, data blocks being transmitted
are specified according to the contents of read block address counter
which carries out successive counting by data block count pulses. The
specified data blocks are sent forth through an AND circuit 108 to the
display device 24 provided in the receiver's terminal section. The display
device 24 indicates data received. Where all outputs from OR circuits
109-111 corresponding to the registers (RCM1 to RCM15) 99-101 have a logic
level of "0", namely, where the code bits stored in said registers are all
indicated in the form of "0000" (that is, under the condition in which
data blocks received are all error-free), then these error-free data
blocks are supplied to the display device 24. To this end, the output
terminal of an NAND gate circuit 112 supplied with output signals from the
OR circuits 109-111 is connected to one of the input terminals of the AND
gate 108. Where even one of the code bits stored in any of the registers
(RCM1 to RCM15) 99-101 is denoted by a logic level of "1", then, the NAND
gate circuit 112 generates an output signal having a logic level of "0",
preventing the contents of the memories (MEMO | | |
