An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match. For a verify procedure an output is generated indicating the first storage location of a search element that is not included in the list of search indicia.

An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAM's), which may be written into, or read from in conventional fashion. In a recognition mode, information is read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor. In accordance with specific aspects of the present invention, masking and/or multiwrite features are provided to permit bit reading/writing/searching, rapid memory writing, to facilitate logical and arithmetic data processing and the like.

A device for the processing of a data base consisting of a sequence of data records, having a reference memory (140) for a reference data record and a mask memory (142) for a mask data record. In reaction to the successively received data of a data record, these memories can be read in order to activate a comparison. There is provided an indicator element (160) which has a state "provisionally correct" and which is activated by a starting signal produced by the reception of a data record. If the comparison indicates that an impermissible relationship exists between the content of an element of the data record received and the corresponding element of the reference data record, the indicator element is set to the state "incorrect". The data record received is meanwhile stored in a data buffer (100,102). At the end of the reception, the state of the indicator element indicates whether or not the data record may be applied to a user. The data buffer may consist of two buffer sections, each for one complete data record, which alternately operate in a read mode and a write mode.

A parallel associative memory provides a way of recognizing or identifying observed data patterns. Each of a plurality of memories stores a plurality of recognition patterns. In response to receipt of a recall pattern to be identified, the recall pattern is contemporaneously compared to the recognition patterns stored in the memories and an exact or best match recognition pattern is selected. In a preferred embodiment, the memories may store multiple data bases each of which includes patterns having different lengths and different radii of attraction. The comparison process is controlled by masks which specify respective portions of the patterns which may include the radii of attraction, bits which must identically match, bits which are ignored, bits which are compared in a bit-wise fashion, and bytes which are compared by multiplication. A correlation is computed and selectively adjusted by the respective radii of attraction. A specified number of the patterns having the best correlation are identified, subject to selected threshold conditions, and sorted according to their respective correlations. The parallel nature of the memory lends itself to a hierarchical organization for increased storage capacity and to parallel processing which increases the speed of the identification or recognition process and thereby allows a broad range of applications. These applications includes fast retrieval of exact or inexact data, diagnosis, image processing and speech recognition.

A hybrid associative memory has a non-associative basic storage and an associative surface. Every data unit individually selectable in the basic storage is sub-divided into sub-units, and a logic unit ALV of corresponding working capacity is provided in the associative surface for every sub-unit. In order for either the sub-units of a data unit or the respectively corresponding sub-units of a corresponding plurality of data units to be connected through to the associative surface as a data unit, the storage of the data units in the basic storage is divided into areas. Every area is formed of a plurality of data units corresponding in number to the plurality of sub-units of the data unit. The sub-units of all data units of an area are ordered in offset fashion therein in accordance with a prescribed classification pattern. The access to a data unit is internally controlled via an address re-ordering unit for the row address in the address controller. The re-ordering of the sub-units within the respective data unit, required to produce the required sequence, is controlled by means of corresponding data reordering units.