Memory system having contiguous storage locations with sequential addresses is partitioned into units to permit separate unit write-in and parallel unit read-out, operations. Each unit is responsive to common word address signals and unique combinations of block address signals. In response to a control signal in a first of two possible states, the memory system operates in a conventional manner, i.e., data is read from or written to a particular location in the memory to or from a data bus, the address of the particular location being supplied over an address bus and having a block select portion and a word select portion. When the control signal is in its second state, each unit is responsive only to the word address signals to read data from or write data to common word locations in each unit simultaneously. Several utilization devices can be similarly arranged so that when the control signal is in the second state, each device is coupled directly to an associated one of the units and all units and devices are decoupled from the data bus. Another embodiment of the invention provides parallel memory access without switching elements. A system is also described which is especially adaptable to color television display of information.
A memory device is constructed having a plurality of output ports, each output port being one word wide, such that a plurality of words may be accessed from the memory simultaneously.
A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
Ragged vertical edges normally displayed by a NTSC color-carrier on a non-interlaced display are effectively eliminated through persistence of vision by altering the duration of a selected single scan-line of the non-display portion of each of successive fields by an odd number of half-cycles of the NTSC color-carrier frequency.
Method and circuit for controlling the color of dot elements in a raster scan display having a data memory for storing the state (on or off) of dot elements which are mapped onto the raster scan display and a smaller auxiliary memory for storing color information. The color information stored in a location of the auxiliary memory specifies the color of a plurality of contiguous dot elements so that the auxiliary memory can be much smaller than the data memory. The contiguous dot elements whose color is specified by a location in the auxiliary memory form a block which can be arranged so that the address bits to the auxiliary memory form a proper subset of the address bits to the data memory.
A graphics data processing system memory is allocatable by software between system memory and graphics framebuffer storage. The memory comprises two-port elements connected in parallel from the RAM port to a controller connected to a bus, and having serial output ports connected to output circuitry to map the storage to a display. Corresponding locations, relative to element origin, in all elements are addressed in parallel as an array. Three modes of memory transactions are all accomplished as array accesses. First, a processor reads/writes the system memory portion by a combination of parallel array access and transfers between controller and bus in successive bus cycles. Second, the controller executes atomic graphics operations on the framebuffer storage using successive array accesses; third, the processor can read/write a framebuffer pixel, by an array access of framebuffer storage with masking of unaddressed pixels. An interface arbitrates among requests for memory access.
