A transistor which has a plurality of ring emitter transistor units formed on a common semiconductor substrate having one conductivity type, each ring emitter transistor unit being provided with a base region of the opposite conductivity type from the semiconductor substrate and formed on its surface, an emitter region of the same conductivity type as the semiconductor substrate and formed in the base region to a depth smaller than the latter to have a ring-shaped plane configuration, a base electrode formed in the vicinity of the outer or inner periphery of the ring-shaped emitter region, an emitter electrode formed in the vicinity of the inner or outer periphery of the emitter region, and a ballasting resistor formed to interconnect the emitter region and the emitter electrode. The product of the area of the emitter region and the resistance value of the ballasting resistor is selected to be in the range of from 6.0 .times. 10.sup.-4 to 1.3 .times. 10.sup.-3 [.OMEGA..multidot.cm.sup.2 ], to provide for enhanced power handling capability of the transistor without a large reduction in its maximum current and to facilitate the design of this kind of transistor.
A bipolar power transistor with improved power dissipation capability. The device is designed to reduce the current crowding that obtains at the edge of a relatively wide emitter because of the debiasing effect of the voltage drop in the base region beneath that emitter. In a preferred embodiment, current crowding is reduced by sub-dividing a typical emitter finger into a central emitting region flanked by two peripheral emitting regions separated from the central region by a resistive portion. The resistive portions are desirably of the same conductivity type as the emitter; this design permits the use of relatively coarse geometries compatible with high yield.
A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.
A novel ring shaped emitter structure with an extrinsic base and base contact in the central portion of the ring is described. This structural configuration is useful for improving the performance of bipolar transistors used in BiCMOS integrated circuits with only minimal changes to conventional CMOS processing technology. A single additional mask is required to form the intrinsic base region of the transistor. The emitter is diffused from a polysilicon layer which also serves as the emitter contact. The polysilicon layer overlies a perimeter portion of an active region defined by an opening in a field oxide and rises up over the field oxide itself. The active emitter region then forms a ring along the perimeter of the active region. The extrinsic base is formed through an opening within the polysilicon layer representing a central portion of the active region. This configuration improves transistor performance by reducing the characteristic spacings and thereby reducing component resistances and capacitances and increasing the cut-off frequency. The improved emitter-base design thereby results in higher bipolar transistor performance in BiCMOS integrated circuits at minimal cost.
The invention relates to a power transistor with a semiconductor body. When shutting off a power transistor, local fusing of the semiconductor body may occur, if a characteristic power loss is exceeded for a certain period of time (second breakdown). This can be avoided, if the transistor includes a multiplicity of small partial transistors with very narrow emitter zones which are mutually paralleled via a ballast resistance each.
A chip carrier for carrying integrated circuit chips is provided. Instead of placing individual circuit components either in the chips or next to them, the components are placed in or near the substrate of the chip carrier. This frees up expensive real-estate for logic chips at the chip level presently occupied by the components. The substrate of the carrier acts as a large heat sink to dissipate power generated by the components.