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What is claimed is:
1. A data driven processor providing program files for performing
designated data processing operations on a plurality of operands applied
thereto, wherein input data containing an operand on which an operation is
to be performed is applied as an input operand file having the format
((A.sub.1) (B.sub.1) (C.sub.1) . . . (N.sub.1) (E.sub.1)) wherein the left
parens are data start characters, the right parens are data end
characters, E.sub.1 is a terminating code indicating the end of the file,
and A.sub.1, B.sub.1, C.sub.1 . . . N.sub.1 are a plurality of fields
contained within the file, one of said fields being a description field
that identifies the file as an operand file, another of said fields
containing an operand on which an operation is to be performed, and
another of said fields containing a program file address corresponding to
one of said program files, and wherein said processor operates in a manner
such that the order and time of performance of said designated data
processing operations are determined by the order and time of arrival of
said operands, said processor comprising:
storage means for storing program information as a plurality of program
files at selectably addressable locations thereof such that the contents
of each program file are accessible in response to the program file
address contained in an arriving operand file, each program file having
the format ((A.sub.2) (B.sub.2) (C.sub.2) . . . (N.sub.2)), wherein the
left parens are data start characters, the right parens are data end
characters, and A.sub.2, B.sub.2, C.sub.2 . . . N.sub.2 are a plurality of
fields contained within the file, one of said fields being a destination
field, another of said fields being an operation code field indicating a
data processing operation, and one or more other ones of said fields being
operand storage fields for storing the one or more operands on which the
data processing operation indicated by the operation code field of the
corresponding program file is to be performed;
logic means responsive to an operation code field accessed from a program
file for performing the indicated data processing operation on one or more
operands applied thereto; and
control means including means responsive to an arriving operand and its
accompanying program file address for determining from the contents of the
operand storage field of the program file corresponding thereto whether
the arriving operand is the last of the one or more operands required for
performance of the corresponding data processing operation;
said control means also including means responsive to a determination that
an arriving operand is not the last required for its corresponding data
processing operation for causing the arriving operand to be stored in an
operand storage field of the corresponding program file;
said control means additionally including means responsive to a
determination that an arriving operand is the last required for its
corresponding data processing operation for causing the arriving operand
and any operands stored in one or more operand storage fields of the
corresponding program file to be applied to said logic means along with
control signals generated in response to the operation code field of the
corresponding program file so as to cause said logic means to perform the
designated data processing operation on the applied one or more operands
and to produce a resultant operand representative thereof.
2. The invention in accordance with claim 1, wherein data is applied to
said processor in a format employing four unique characters each of which
is represented by a unique pair of binary bits, said four unique
characters comprising a "1" character, a "0" character, and said data
start and data end characters.
3. The invention in accordance with claim 1, wherein said logic means and
said control means recognize the end of an operand file in response to the
detection of the terminating code thereof and recognize the start and end
of a field in response to detection of the left and right parens provided
at the beginning and end thereof.
4. The invention in accordance with claim 1, wherein said processor
includes output means operating in conjunction with said control means for
providing an output operand file having the same format as an input
operand file and containing a resultant operand produced by said logic
means in response to a data processing operation, said output operand
including a destination address derived from the destination field of the
program file whose operation code field was used to produce the resultant
operand.
5. In a data processing system including at least one processor, a method
of driving said processor such that the order and time of performance of
data processing operations are determined by the order and time of arrival
of the operands to be processed, said method comprising:
applying input data containing an operand on which an operation is to be
performed to said processor as an operand file having the format
((A.sub.1) (B.sub.1) (C.sub.1) . . . (N.sub.1) (E.sub.1)) wherein the left
parens are data start characters, the right parens are data end
characters, E.sub.1 is a terminating code indicating the end of the file,
and A.sub.1, B.sub.1, C.sub.1, . . . N.sub.1 are a plurality of fields
contained within the file, one of said fields being a description field
that identifies the file as an operand file, another of said fields
containing an operand on which an operation is to be performed, and
another of said fields containing a program file address;
storing program information in said processor as a plurality of selectably
addressable program files having the format ((A.sub.2) (B.sub.2) (C.sub.2)
. . . (N.sub.2)), wherein the left parens are data start characters, the
right parens are data end characters, and A.sub.2, B.sub.2, C.sub.2 . . .
N.sub.2 are a plurality of fields contained within the file, one of said
fields being a destination field, and another of said fields being an
operation code field indicating a data processing operation;
determining in response to the receipt of an arriving input operand file
whether it contains the last of the one or more operands required for
performance of the data processing operation indicated by the operation
code field contained in the program file corresponding to the accompanying
program file address;
storing the arriving operand in response to a determination that it is not
the last of the operands required for performance of the corresponding
data processing operation; and
performing the corresponding data processing operation in response to
determining that the arriving operand is the last of the one or more
operands required for performance thereof.
6. The method in accordance with claim 5, wherein said method includes
outputting an output operand file from said processor having the same
format as an input operand file and containing a result operand produced
by said logic means in response to a data processing operation along with
a destination address field derived from the destination field of the
corresponding program file whose operation code field was used to produce
the resultant operand.
7. The invention in accordance with claim 6, wherein one or more of said
fields contained in a program file are operand storage fields for storing
the one or more operands required for performance of the corresponding
data processing operation, and wherein the step of determining includes
accessing the one or more operand storage fields of the program file
corresponding to the program file address of an input operand file to
determine the presence of the operands required for performance of the
corresponding data processing operation. |
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Claims |
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Description |
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CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to the following copending applications:
1. Ser. No. 447,016, filed Feb. 28, 1974, for a Data Driven Digital Data
Processor.
2. Ser. No. 447,015, filed Feb. 28, 1974, now U.S. Pat. No. 3,886,533, for
Vocabulary and Error Checking Scheme for a Character-Serial Digital Data
Processor.
3. Ser. No. 447,034, filed Feb. 28, 1974, for Nested Data Structures in a
Data Driven Digital Data Processor.
4. Ser. No. 446,912, filed Feb. 28, 1974, for Recursive Mechanism in a Data
Driven Digital Data Processor.
BACKGROUND OF THE INVENTION
The present invention relates generally to improvements in digital data
processors, and more particularly pertains to new and improved digital
data processor systems wherein the data processor is a microprogrammed
integrated circuit device.
In the field of digital data processing it is presently the practice to
employ system architectures that evolved under the influence of high
hardware cost. This constraint resulted in centralization of system
control into devices referred to as the central processor and main memory
units. Because of this massive and expensive centralized hardware which
needed to be controlled, operating systems (master control programs) were
evolved to generalize its utilization, by sharing it across a number of
programs or tasks. The system architectures which resulted from these
influences are highly generalized and as a result, are unnecessarily
complex, ad hoc, and inefficient with respect to a large number of
particular situations. This type of architecture is partitioned in an
irregular manner and is implemented principally by hardwired sequential
logic. Where micro-programming techniques are utilized, the basic system
functional architecture is not changed in that the micro-coded processors
still follow register oriented clocked sequential architectures.
The new integrated circuit technology, such as MSI and LSI which provide
the essential elements of a data processor on a single chip can be
utilized effectively only if a new set of design constraints is followed.
LSI technology, for example, requires hardware regularity and
non-dedication of specialized or complex algorithms to circuit chips.
Additionally, since integrated circuit memories are interface compatible
with integrated circuit logic, the register oriented processor
architecture scheme may be eliminated by distributing the system circuit
memory through the system. This, of course, eliminates the need of a
centralized main memory subsystem. Now that it is feasible to distribute
system memory throughout a system, it is desirable to eliminate the
previously required central control operating systems.
To be able to utilize LSI technology effectively, a system architecture
which results in a well-formed and regular partitionable system is
required. Even though nearly all microprogramming techniques utilized in
the past have this underlying objective, prior art programming techniques
have failed to produce a system which is efficient to program and
efficient in execution of its algorithms. In other words, these prior-art
microprogrammed systems exhibit a total lack of continuity between what
the machine language is and what the user programming needs and language
demands are. This is true because the prior-art machine microcode
languages are serial and binding in nature which is in direct opposition
to the LSI technology demands for regularity, and nonbinding of complex
functions.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a digital processor that may
be used as a basic building block in a multi-processor computer.
Another object is to provide a digital processor for use as a building
block in multi-processor computers that does not need to utilize a master
control program or require an extensive interrupt system.
A further object of this invention is to provide an electronic digital
computer that has improved emulation capabilities.
These objects and the general purpose of this invention are accomplished by
utilizing a multi-character vocabulary in a character-serial data
processor wherein two of the characters are used to define the start and
end of a particular data field. Each character is represented by a
plurality of binary bits. The data structures are organized into data
files containing fields in a manner that permits for the expansion and
contraction of these fields. The structure and organization of a file is
described by the contents of the first field in that file. A program or
process is carried out in response to the linking up of pairs of data
files, each pair having one data file containing a part of the program,
and the other data file containing the operands for that part of the
program. Either type of data file may be resident in the data processor's
storage area (static) while the other is supplied to the processor from
the outside (dynamic). Arrival of the dynamic data files causes the mating
data file in storage to be addressed. The two mated data files are used in
combination to produce the resultant dictated by the program data file.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and many of the attendant advantages of this invention will
be readily appreciated as the same becomes better understood by reference
to the following detailed description when considered in conjunction with
the accompanying drawings in which like reference numerals designate like
parts throughout the figures thereof, and wherein:
FIG. 1 is a block diagram illustration of a single processor data
processing system, according to the invention.
FIG. 2 is a logic diagram of the input queue in the processor of FIG. 1.
FIG. 3 is a logic diagram of the vector logic unit in the processor of FIG.
1.
FIG. 4 is a logic diagram of the control unit of the processor of FIG. 1.
FIG. 5 is a logic diagram of the output queue of the processor of FIG. 1.
FIG. 6 is a logic circuit of a signal recognition circuit utilized in the
input queue of FIG. 2.
FIG. 7 is an abstract illustration of a four-character vocabulary utilized
by the processor of FIG. 1.
FIG. 8 is an abstract illustration of the general structure of a data file
utilized by the processor of FIG. 1.
FIG. 9 is an abstract illustration of a general data structure file that
has subfiles within it.
FIG. 10 is an abstract illustration representing in tree form a particular
example of a program that may be executed by the computer of FIG. 1.
FIG. 11 is an abstract illustration of a simple algorithm represented in
tree form and the data structure or file representing that algorithm that
is utilized by the processor of FIG. 1 to perform the specified
operations.
FIG. 12 A and B is an abstract illustration of a specific example of the
interaction of program and operand data structures within the various
major parts of the processor of FIG. 1 to produce a desired result.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1, illustrates a one processor data driven processor system
communicating with a plurality of peripheral units 15, 17, 19 through an
input/output exchange 13. The input/output exchange 13 may be a standard
type of switching circuit such as that used in telephone exchanges in
which any one of the peripheral units may be connected to the data driven
processor 11 by way of input cable 31 or output cable 33. The peripheral
units may be parallel or serial format units. To accommodate the character
serial nature of the processor 11 when parallel format units are utilized,
the input/output exchange 13 would include a multiplexor to convert the
plurality of parallel signal paths coming from the peripheral units 15,
17, 19 to the relatively serial signal path input to the processor 11. To
accommodate the character-serial signal transmission from the processor 11
to the parallel format peripheral units 15 through 19, the input/output
exchange 13 would include a demultiplexor. Peripheral units 15, 17, 19 may
be any of the well known devices, such as, magnetic tape drives, card
readers, card punch units, keyboard units, printers, or drum or disk
storage devices.
The data driven digital computer or data processor 11 receives data
structures from the peripheral units at its input queue 21. These data
structures, as will be hereinafter explained, have a specialized
organization and must follow certain syntax rules. The input queue 21 is
basically a FIFO (first-in-first-out buffer unit) which performs the
additional function of synchronizing the asynchronous data structures
received on the input cable 31 to the system clock of the computer 11. The
data structures received by the input queue 21, are received character
serially. A commercially available FIFO buffer which may be adapted for
use in the input queue 21 is disclosed in the Signetics Corporation 1972
parts catalogue, pages 7-135 to 7-138.
These data structures may be thought of as being communicated to the other
elements of the processor 11 in a character-serial manner. Data structures
in the input queue 21 are transmitted to computer storage 25, for example,
in a character-serial manner over cable 35, to a control unit 23, and from
the control unit 23 over cable 51 to computer storage 25. The control
communication between the input queue 21 and control unit 23, over cable
37, and the control communication between the control 23 and the storage
25, over cable 49, will be hereinafter explained.
Besides data structures from the input queue 21 being transmitted to the
storage 25, they may be transmitted to a vector logic unit 27 by way of
control 23 over cable 47. Likewise, data structures from the storage 25
may be communicated to the vector logic unit 27 by way of control unit 23,
over cable 45. Control communication between the vector logic unit 27 and
the control unit 23, by way of cable 43, will be explained hereinafter.
Vector logic unit 27 is basically a serial arithmetic unit that performs,
for example, such basic functions as addition, subtraction, compare and
send-to on variable field length data structures. The vector logic unit
may communicate directly with the storage 25, over data cable 53, and with
an output queue 29, over data cable 59. The control communication between
the vector logic unit 27 and the storage 25, over control cable 55, and
with the output queue 29, over control cable 57, will be hereinafter
explained.
The computer storage 25 of the data driven computer 11 may be a random
access integrated circuit memory of a preferred size constructed from
random access memory chips such as manufactured by the Signetics
Corporation, for example. In their 1972 parts catalogue on page 4-24,
Signetics Corporation lists a 32 by 2 random access memory chip that may
be utilized in constructing the storage 25. The construction of a larger
size memory with such a memory chip is considered as well within the
purview of a person of ordinary skill in the art. Another example of a
memory chip that may be utilized to build the storage 25 can be found in
the 1972 Signetics catalogue on page 4-13 which illustrates a high speed
content addressable memory chip.
The output queue 29 which may receive data structures from the vector logic
unit 27, storage 25, or the input queue 21 performs the function of
placing the data structures it has received into a form that may be
transmitted to the peripheral units 15-19 by way of the I/O exchange 13.
The output queue, like the input queue, is basically a FIFO buffer,
accepting data structures in a character-serial manner and transmitting
these characters to the I/O exchange.
Referring now to FIG. 2, the input queue 21 communicates with the I/O
exchange over cable 31. Cable 31 is made up of lines 79, 81, 83 and 85
which eminate from or lead to interface logic 61 in the input queue 21.
Lines 85 are two parallel data lines that receive two bits in parallel
from the I/O exchange (FIG. 1). These two parallel bits represent a
character. The other three lines 79, 81 and 83 are control lines between
the input queue and the I/O exchange. Line 79 transmits a binary signal
level that instructs the I/O exchange to retransmit the data structure
whenever an error has been detected in the previously received data
structure. Line 81 carries a binary signal level that enables or disables
the I/O exchange in regard to the transmission of data structures. Line 83
carries a signal level generated by the I/O exchange which indicates a
request to send data structures from one of the peripheral units or the
output queue of the data processor 11. It would be in response to such a
request signal level that the signal level on line 81 would enable the I/O
exchange, if the input queue could hold additional data.
The character serial data structure received on lines 85 from the I/O
exchange 13 (FIG. 1), besides being submitted to the interface logic 61 is
checked for errors by logic circuitry, for convenience called "paren"
recognition logic, and a binary up/down counter 65 that responds to the
"paren" recognition circuit 63. The count of counter 65 is transmitted to
the interface logic 61 over cable 93. Suffice it to say for the present,
if the count of the binary up/down counter 65 at the end of a particular
data structure is not zero, interface logic 61 requests a retransmit over
line 79 because an error occurred in the data structure. The specific
logic of paren recognition circuit 63 and its interaction with up/down
counter 65 and the interface logic 61 will be explained more fully
hereinafter.
As was noted above, the input queue 21 basically functions like a FIFO
buffer and synchronizes the asynchronous incoming data characters with the
computer system clock (not shown) that is part of the interface logic 61.
The buffer portion of the input queue is the input queue memory 67 which
may be a random access memory built from integrated circuit random access
memory chips manufactured by the Signetics Corporation and listed in their
1972 parts catalogue on page 4-20.
The data characters received on lines 85 from the peripheral units are
transmitted to the input queue memory 67 over lines 96 where they are
stored in the next available space as indicated by the write pointer
circuit 73. In between the storing of data characters in the input queue
memory, data characters are being read out of this memory and transmitted
to the other components of the processor 11 (FIG. 1) by way of the control
unit 23 (FIG. 1). The particular data character that is read out of the
memory 67, at a certain instant in time, is determined by the read pointer
circuit 71. The data character that is read out of the input queue memory
is transmitted from the input queue memory over lines 98 to the interface
logic 61 and then to the control unit 23 (FIG. 1) over lines 35. The
control lines 123, 121 making up the control cable 37, carry read enable
and read request signals from the control unit 23 (FIG. 1). Line 123
carries a read enable signal. Line 121 carries a read request signal.
Generally speaking, then, information is being stored into the input queue
memory 67 as fast as it is received and it is being read out from the
input queue memory 67 in a FIFO order as fast as the control unit 23 (FIG.
1) is calling for it. As the interface logic 61 receives data characters
over lines 85, it generates a signal on line 97 to a memory cycle control
unit 69 indicating that a write function is required. Memory cycle
control, in response to this write request generates a write enable
signal, on line 103, to the input queue memory 67, a write select signal,
on line 105, to a selector 75, and an increment signal, on line 99, to a
write pointer 73.
Selector 75 may be of the type manufactured by the Signetics Corporation
and described in their 1972 parts catalogue on page 2-136. Basically, the
selector, in response to a write or read select signal on line 105 chooses
the write or read pointer output signal supplied to it on cable 109 and
111 respectively, to transmit over cable 107 to the address register of
the input queue memory 67.
The write pointer 73 and read pointer 71 may be a binary counter
manufactured by the Signetics Corporation and listed in their 1972 parts
catalogue on page 2-100. The incrementing inputs 99, and 101 to the write
pointer and read pointer, respectively, from memory cycle control 69 would
be connected to the A input (not shown) of these Signetics counters. Line
100 from interface logic 61 to both the read pointer 71 and write pointer
73 would be connected to the reset inputs (not shown) of these counters.
The outputs of both the write pointer and read pointer, besides going
through the selector to address the input queue memory 67, are sampled by
a comparator 77. The comparator may take the form of a comparator circuit
manufactured by the Signetics Corporation and illustrated in their 1971
TTL/MSI parts catalogue on page 101. This comparator has two output leads
which indicate which of the two inputs is larger, and when they are equal.
Because the input queue 67 is functioning as a FIFO, that is, a first-in
first out buffer, the write pointer count will always be greater than the
read pointer count, whenever the input queue memory 67 had data therein
but is not full. Therefore, a signal on line 119 from comparator 77 will
indicate to interface logic 61 that the write pointer count is greater
than the read pointer count. This indicates to the interface logic that
data still remains in the input queue memory.
Whenever the write pointer count equals the read pointer count, a signal is
transmitted from the comparator, over line 117, to the interface logic 61.
This signal can mean that the input queue memory 67 is either completely
empty or completely full, depending upon whether the last memory request
generated by the interface logic 61 was a read or write request. The
interface logic 61 interprets the signal on line 117 as meaning that the
input queue memory 67 is full if the last memory operation was a write
operation. If the last memory operation was a read operation, a signal on
line 117 is taken as an indication that the input queue memory is empty.
The synchronization logic 61 knows if the last memory operation was a
write or read operation since it transmitted either a write or a read
request over lines 97, 95, respectively, to the memory cycle control 69.
Whenever the interface logic 61 determines that the input queue memory 67
is empty, it generates a reset signal on line 100 to be supplied to both
the write and read pointers.
The specific logic circuitry of the memory cycle control 69 and interface
logic 61 will not be discussed herein because the implementation of the
functions herein attributed to these logic circuits is viewed as well
within the purview of a person of ordinary skill in the art.
Referring now to FIG. 3, a serial vector logic unit 27 that may be utilized
in the computer of FIG. 1 is illustrated as consisting basically of two
ROMs (read-only memories) 125 and 129. Both ROMs may be of the type
manufactured by the Signetics Corporation and listed in their 1972 parts
catalogue on page 4-1. Address registers 124 and 128 for the read only
memory 125 and 129, respectively, are standard parallel in parallel out
address registers. The only structural difference between the two read
only memories resides in the micro-code contained within them. Read only
memory 125 contains the micro code required for generating the results of
dyadic operations such as, addition, subtraction, or compare, for example.
Read only memory 129 contains the micro-code required to generate the
result of monadic operations such as complement, delete first bit, or
first bit to zero, for example.
Data structures coming character-serially from the storage 25 of the
computer 11 (FIG. 1) by way of the control unit 23 over lines 45 to the
vector logic unit 27 are directed by demultiplexor 135, according to a
control signal on line 43a from the control unit 23, to the dyadic ROM 125
over line 139, or the monadic ROM 129 over line 142, depending upon what
kind of data structure is being addressed by the data structure in the
input queue 29. This will be more fully explained hereinafter.
Likewise, the demultiplexor 137 receives character-serial data over lines
47 from the input queue 21, by way of control unit 23, and routes it
either to the dyadic ROM 125 over line 141 or the monadic ROM 129 over
line 143. The output of either the dyadic ROM 125 or the monadic ROM 129
will be routed to the storage 25 of the computer or to the output queue 29
of the computer (FIG. 1), depending on the destination address contained
within the program data structure. This destination address is supplied to
demultiplexors 133 and 130 over lines 43d by the control unit 23 of
computer 11 (FIG. 1).
The demultiplexors 135, 137, 130, and 133 utilized in this vector logic
unit may be of the type manufactured by the Signetics Corporation and
illustrated in their 1972 parts catalogue on page 2-132.
Assuming, for purposes of example, that a dyadic operation were to be
performed, an operand A being summed with an operand B, an OP code
designating the dyadic operation of addition would be supplied to the
address register 124, either from the storage 25 or the input queue 21 of
the computer, for reasons which will be hereinafter made clear. Along with
this OP code, the two operands are also supplied, character serially, to
the address register 124. As a result, the output on cable 129 of the read
only memory 125 would be the character serial results of the summation of
the two operands. Effectively, what is occurring is the OP code, in
addition to the operands, act as addresses to the particular areas in the
read only memory 125 that are storing the results of the summation of a
particular two characters from the two operands being summed.
The output of the read only memory 125, in this particular example, would
also contain a signal on line 43c that would indicate to the control unit
23 (FIG. 1) that a particular character summation has been completed.
Also, in the case of addition, carry signals are propagated back to the
input of the read only memory 125 on lines 132 to modify the next
character addition. In case of monadic operations being performed with
read-only memory 129, feedback lines 131 may simply be a stepping counter
input to modify the contents of the address register 128 of the monadic
ROM so that the next memory location is addressed.
In summary, the control unit 23 introduces data structures from the storage
25 and the input queue 21 to the vector logic unit 27 which responds to
these two data structures by generating a result plus control signals,
which are sent back to the storage 25 over lines 53 and 55, or to the
output queue 29 over lines 57 and 59.
Refer now to FIG. 4 which illustrates the control unit 23 of computer 11 to
be a microprogrammed unit consisting of a plurality of read-only memories
and multiplexors. The field analyzer ROM 146 receives data structures from
the input queue, over lines 35, or from storage, over lines 51b. Either
the data structure from the input queue 21 (FIG. 1) or the data structure
from storage 25 (FIG. 1) addresses the field analyzer ROM 146 through
address register 145 causing the field analyzer ROM 146 to respond by
sending control signals to one of the plurality of demultiplexors 148, 150
and 152.
For example, if the data structure coming in on line 35 from the input
queue (FIG. 1) happens to be an operand file, the field analyzer would
direct the demultiplexor 148 to transmit the operand fields over one of
the three lines 47a, 39a or 51a, line 47a leading to the vector logic
unit, line 39a leading to the output queue, and line 51a leading to the
store. The field analyzer would, in this instance, be responding to the
description field in the operand file. Likewise, if a data structure
coming in on line 51b from storage (FIG. 1) happens to be an operand file
or field, the field analyzer ROM 146 would direct the demultiplexor 152
over line 162 to transfer the data over line 39b or line 45, line 39b
leading to the output queue and line 45 leading to the vector logic unit.
Assuming now that instead of an operand data structure being received on
either lines 35 or 51b, a program data structure is received. This program
data structure would address the field analyzer ROM 146 causing it to
transmit an address to one of the ROMs 154, 156, 158, by way of
demultiplexor 150. The ROMs 154, 156, 158 make up a microprogram library
that contains particular microprograms. These microprograms are addressed
by the data structure coming in on either data lines 35 or 51b. Assuming
that the data structure received by the field analyzer ROM 146 starts out
with a field that indicates that what is to follow is a program file, the
field analyzer would generate a plurality of signals to the demultiplexor
150 that would route the signals to the program file ROM 154, for example.
In response to these signals addressing particular areas in this ROM,
control signals are generated, over lines 43, to the vector logic unit
(FIG. 3), over line 41b, to the output queue (FIG. 5), o | | |
