In a computer system operating under read only memory control and having a keyboard, a video terminal, and a port device in the form of a tape recorder/player, an improved apparatus for alpha-numeric/graphic display in which the outputs of respective character and graphic generators couple to respective first and second shift registers with the shift registers being controlled by first and second gate means in a manner to enable clocking of the first shift register when the type code indicates alpha-numeric display and enabling clocking of the second shift register when the type code indicates graphic display.

The present invention relates to a decoder for converting compiled page information supplied in code into information which can be directed to a raster output scanner in the form of a serial pixel bit flow.

A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

A scanning CRT visual display system is provided in which the operation of the CRT controller which provides video blanking pulses and horizontal and vertical sync pulses for controlling the CRT display is temporarily halted when a larger than normal vertical spacing between horizontal scan lines is desired. During the time that the operation of the CRT controller is halted, which is accomplished by the selective blocking of clock timing pulses to the controller, an auxiliary synchronous counter circuit effectively counts the clock timing pulses and provides a substitute horizontal sync pulse for the CRT display such that during the implementation of a larger than normal vertical step for the scanning CRT display system, horizontal sync pulses are always provided even though the operation of the CRT controller is temporarily suspended during this time.

A circuit for controlling attributes of a plurality of characters on a display. The circuit has a processor for controlling transfer of data associated with characters to be displayed and a communications device connected to the processor. A display controller is also provided for controlling the display of characters. An external controller is connected to the communications device and to the display controller for providing attributes corresponding to the displayed characters. The external controller also has provision for controlling the display of a set of characters in addition to the set normally controlled by the display controller.