A dynamic memory is disclosed, in which data is rearranged among its internal memory locations in accordance with either of two different shuffle operations. The shuffle operations, an In Shuffle and an Out Shuffle, rearrange the data in a manner similar to the manner in which cards of a deck are rearranged when shuffled. Using only the two shuffle operations, a method of random accessing data in the theoretical minimum time is disclosed, for all odd-sized memories and all memories of size 2.sup.r. Once a desired datum has been accessed, successive data can be sequentially accessed in unit time. Processes for sequential accessing of data are shown to be related to the existence of sequences of In and Out Shuffles which move each datum through the read/write window of the memory, which sequences are defined as tours. A method for determining the existence of and for constructing tours for certain sized memories is also disclosed. An address register that keeps track of the current address of the datum appearing in the index window of the memory, which is sufficient to define the entire memory configuration, operates in conjunction with control means to calculate I-O sequences for random accessing of data.
A plurality of memory blocks, which includes a plurality of memory areas, each having a page number. Each of the memory blocks has a set number. A page controlling register stores mapping information and a page number of the memory areas. A mapping register stores mapping information including set information that indicates the set number of a memory block in which data supplied from a CPU is stored. A memory controller accesses the memory section in accordance with the mapping information.
A method of emulating a sequential data storage device on a random access device to permit the transfer of information in a sequential format between a host computer and a random access storage media. Commands for storing information in the sequential format from the host are transformed into commands to store data on the random access media. Commands for retrieving information in a sequential format are provided by the host to retrieve the stored information from the random access media. The commands for retrieving information are transformed into commands that retrieve the data on the random access media. Once the data is retrieved, it is then provided to the host.
In a named data processing system having a plurality of memory modules, each module therein having a plurality of locations for storing data pages and the like, a memory address translation apparatus and method translates a data job name and associated segmented address field into a memory module-page addressing pair wherein each and every storage location may be accessed by each and every job name. The job name and the associated segmented address field are each partitioned into most and least significant bit fields. Through translation a storage location is defined by the exclusive ORing of the least significant fields of the data job name and segmented address field. Likewise a memory module is defined by the exclusive ORing of the most significant fields of the job name and the segmented address field as permuted by an exclusive ORing with the least significant field of the segmented address field. Preferably, in order to increase address spacing activity, the most significant field of the job name is processed through a Fibonacci hashing process before any exclusive ORing process.
An apparatus for simulating a logic circuit is disclosed comprising a first plurality of logic block circuits for simulating portions of the logic circuit the logic block circuits having a predetermined number of inputs and outputs; at least one routing logic block for routing signals between the logic block circuits; each of the logic block circuits further including: a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding the logic block circuit; and a second series of input scan chain units for storing and inputting a signal to each of the logic block inputs; each of the scan chain units being further interconnected to the routing logic block for the storing of the input signals and the output signals to and from the routing logic block. Further, the scan chain units can preferably comprise a series of serially interconnected storage units and the interconnection of the routing logic can preferably comprise a serial interconnection between one of the storage units and the routing logic. Ideally, the storage units comprise flip flops each interconnected to a master clock signal input. The output scan chain units can include a multiplexer connected between the signal outputs and a corresponding storage unit the multiplexer multiplexing the signal output and the output of an adjacent storage unit.
The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.
