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Document Number
US Patent 4161664
Issued Date
July 17, 1979
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Abstract
An input circuit has at least an enhancement type first MISFET incorporated between an input terminal and a power supply terminal for the input circuit. A gate electrode of the first MISFET is connected to the power supply terminal, and at least a second MISFET is incorporated between the input terminal and a gate electrode of a third MISFET constituting the input circuit. A gate electrode of the second MISFET is connected to the power supply terminal, whereby the dielectric breakdown of the gate of the third MISFET is prevented.
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Input circuit - US Patent 4161664 Drawing
Drawing from US Patent 4161664
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Number of Claims:
6
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Owner
Published
July 17, 1979
Application Number
05/879,756
Filed
February 21, 1978
US Classification
327/581   327/546
Int'l Classification
H03K   19/0185   (20060101)   H03M   11/00   (20060101)   H03M   11/20   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
The present application is a Continuation of application Ser. No. 643,771, filed Dec. 23, 1975, now abandoned.
Priority Data
Jan 06, 1975 [JP] 50/000103
USPTO Field of Search
307/202   307/205   307/214   307/237   307/251   307/296   307/297   307/304   307/DIG.1   361/56   361/90   361/91   357/41   340/365E   340/365S   445/1  
Related Patents
4489245 - D.C. Voltage bias circuit in an integrated circuit - Owned by Kabushiki Kaisha Toshiba (JP)

In an integrated circuit having an amplifier with its input terminal connected to a signal input terminal, a D.C. voltage bias circuit is provided which includes a D.C. bias voltage generator and a depletion mode MOS transistor connected at its source-drain path between the bias voltage generator and the signal input terminal and coupled at its gate electrode to either its source or its drain thus preventing breakdown of the gate insulating film of the depletion mode MOS transistor resulting from a surge voltage from the signal terminal.

Claims
Description
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