A data processing system includes a number of input/output devices coupled to a communication multiplexer which polls the devices in a predetermined order. Apparatus in the communication controller rearranges the polling order to provide highest priority to an input/output device in a receive mode that is currently operative and to give lowest priority to an input/output device in a transmit mode that has just completed its operation.

A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that has writeback cache. The control module also maintains coherency between main memory and cache in a writeback subsystem.

A device for reducing access time to RAM arrays, especially DRAMs, by including fast access cache rows, e.g., four rows, to store data from accessed rows of the array, where data can then be accessed without precharging, row decoding sensing, and other cycling usually required to access the DRAM. Address registers, comparators, and MRU/LRU register and other cache control logic may be included in the device. The device allows parallel transfer of data between the RAM array and the cache rows. The device may be constructed on a single chip. A system is disclosed which makes use of the cache RAM features in a data processing system to take advantage of the attributes of a cache RAM memory.

A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes. After a cache miss, although the central processor must be stopped to permit updating, it can resume operations a cycle earlier than is possible without the divided cache cycle.

There is provided a microprocessor interface circuitry which allows single peripheral and memory devices to be used with at least two different types of microprocessors. The interface includes a latch which latches the state of a control signal provided to the peripheral/memory device by the microprocessor. The control signal that is latched serves a somewhat different function when eminating from each of the at least two different microprocessors, and as such has different logic states. Logic circuitry is controlled by the latch to take at least one other control signal and generate the internal control signals used by the peripheral/memory device.