A novel universal multi-mode programmable two-channel timing generator employs a plurality of counters and logic circuitry. An input chip counter is coupled for receiving system clock signals and producing chip strobe and other output timing signals which are programmably capable of generating different rates of operation and different data or PN rates on different channels as well as different I and O enable signals for dedicated tracking and timing signals. The signals produced are used for synchronous-sample or non-synchronous-sample operation in a simple fast acting circuit designed for VLSI implementation.

In an apparatus and a method for recognizing the start of a noise-corrupted received telegram signal, and wherein the telegram signal consists of an information-containing sequence of bits ahead of the telegram signal, thereafter transmitting an intermediate sequence of bits following the preliminary sequence, but still ahead of the telegram signal, wherein the preliminary and the intermediate sequences are correlated with different parts of the preliminary and of the intermediate sequence in a pre-arranged manner, and detecting the pre-arranged manner so as to positively signal termination of the intermediate sequence; recognition of the start of the telegram signal is thereby ensured.

A clock regenerator generates a clock Co synchronized with an input data pattern and a data pattern generator generates a reference data pattern in synchronization with the clock Co. The reference data pattern and the input data pattern are compared by a data disagreement detector to detect disagreement therebetween. The disagreement detection signal thus obtained is frequency divided by a 1/m-frequency divider and its frequency-divided output is further frequency divided by a 1/-n frequency divider. The frequency-divided output of the 1/n-frequency divider is provided to a bistable flip-flop, placing it in one stable state. The logical sum of the output of the flip-flop in the one stable state and the 1/m-frequency divider is obtained, as an inhibit pulse, by an AND gate, and the inhibit pulse is applied to another AND gate to inhibit the passage therethrough of the clock Co to the data pattern generator, delaying the generation of the reference data pattern in the data pattern generator. The 1/m-frequency divider, the 1/n-frequency divider and the flip-flop are reset every k pulses of the clock Co.

A receiver, for receiving a signal comprising a carrier signal modulated with a digital signal, comprises a circuit for demodulating the received signal to produce an output signal which contains the digital signal. Because of repeated filtering, the digital signal is typically in the form of an approximately sinusoidal signal, which has a component whose frequency is equal to half the basic bit rate of the digital signal: because of noise, this component is subject to considerable timing jitter. To overcome this, the output signal is digitized and applied to a digital correlator, where it is correlated with a reference signal whose frequency is also equal to half the basic bit rate of the digital signal. The reference signal is preferably derived from a phase-locked loop locked to the carrier frequency. The correlator, which is constituted by a microprocessor, determines the instants of time which most nearly coincide with the mean-level crossing points of said component (which instants correspond to transitions between one bit of the digital signal and the next), and also determines successive bit values on the basis of the coincidence determination. The receiver can be used to receive mains-borne signals, i.e. signals transmitted over an electrical power supply network, or radio broadcast signals.

A precorrelation digital spread spectrum receiver includes a signal converter for amplifying and directly converting RF band spread spectrum signals received by an antenna to a digitized baseband signal comprising a sequence of N-bit quantized baseband values. The baseband signal is a linear composite signal containing signals from all satellite channels as well as noise and jamming. An N-bit digital correlator correlates successive N-bit baseband signal values with successive local code values to produce plural correlation signals. A vector processor processes the correlation signals to derive early, late and on-time code correlation signals. The processed correlation signals are accumulated to provide process gain and are used to form error signals for carrier and code tracking, and measurement purposes. A sequential-tracking multi-channel embodiment time shares a common set of circuit elements and digital processing instructions to successively track different channels. In a preferred embodiment, the vector processor uses micro-code instructions to remove the carrier Dopler shift by multiplying the correlation value with a stored complex constant corresponding to the Doppler contribution. The receiver provides coarsely quantized code delays to the correlator, and uses digital interpolation routines to estimate correlation values for code delays of interest, thus providing fine resolution in the code delay without using either a numerical control oscillator or crystal oven.