Information is selectively exchanged between a number of closely located stations and a number of remote stations. Signals are coupled between the close stations via a first, parallel data channel. A second, serial data channel connects a common adapter circuit for the closely located stations to the remote stations. Each of the stations includes a data module for coupling signals between the first data channel and plural peripheral devices at the station. Each of the modules includes a data processing unit having a memory that stores a program dependent on the configuration of the peripheral devices at the station. Each of the data processing units derives an enabling order for a module at another station, which enabling order is coupled to the another station via the first station or via the first station, the adapter circuit and the second channel; the enabling orders cause the programs stored in the memories to be executed. Signals are exchanged between the data processing units in response to a succession of information exchange controls by the modules of all of the stations.
RELATION TO CO-PENDING APPLICATION
The present application is a continuation-in-part of and improvement on systems of the type disclosed in Ser. No. 521,021, filed on Nov. 5, 1974 for "Device For Selective Exchange Of Information" and relates to an improvement on control modules for information transferred between remotely and closely spaced stations containing data emitters and receptors.
An industrial communications network includes microprocessor-based interface circuits which each connect a controller such as a programmable controller to a high speed serial data link. Each interface circuit connects to the data link and its associated controller, and each is operable to receive messages on the data link directed to its associated controller. In addition, each interface circuit can assume mastership of the communications network when the existing master generates a poll command indicating it is ready to relinquish mastership. As a result, the communications network will continue to function even though one or more controller or their associated interface circuits become inoperable.
An interface circuit for a programmed controller disposed between the CPU of the programmed controller and an input/output unit includes eight N.times. 1-bit RAMs with simultaneous operating switching circuits for accessing the RAMs in parallel by the input/output unit and with sequential operating selecting circuits for accessing the RAMs serially by the CPU, whereby the interfacing process is sped up.
A primary storage control unit receives an information unit from a remote host over a fibre channel connection. The primary storage control unit adjusts an information unit pacing parameter included in a response sent from the primary storage control unit to the remote host, wherein the information unit pacing parameter indicates the number of information units that the remote host is allowed to send to the primary storage control unit without waiting for any additional response from the primary storage control unit.
An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.
This invention relates to an adapter for interprocessor communications and the method therefor. An adapter is included in a data processing system which has a plurality of central systems, each of the plurality of central systems having at least one serial channel control processor. The data processing system further has a dynamic channel exchange for providing switching logic thereby permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The adapter is operatively connected to the dynamic channel exchange for providing communications between any pair of central systems. The adapter comprises a link control module which provides handshake control to perform message bit/byte synchronization and translation. A message protocol module, which is operatively connected to the link control module, controls the transmission of information with a selected one of the plurality of central systems, the control being administered by interfacing with the serial channel control processor in accordance with a defined message protocol. A data buffer provides intermediate storage of information passed between the pair of central systems. A control processor schedules and monitors the information transfer into and out of the data buffer by interfacing with the message protocol module in accordance with the defined message protocol thereby achieving the information transfer between the pair of central systems.
