The horizontal-deflection pulses (HA) and the vertical synchronizing pulses (VS) are applied to the count input (Ez) and the reset input (Er) of an upcounter (VZ) whose count outputs are connected to the address inputs (Ea) of a programmable read-only memory (PROM1) via a decoder (DC). The S-shaped characteristic of the deflection-stage current is approximated by portions of constant slope whose associated slope values are stored in the programmable read-only memory (PROM1) under one address each. The pulses of a clock generator (TG2) whose frequency is chosen so that when a first presettable down-counter (RZ1) is set to the highest slope value, its zero state is reached within line period are applied via one of the input-output paths of an AND gate (UG1) to this first presettable down-counter (RZ1), which is preset by the programmable read-only memory (PROM1) via first input-output paths of a multiple AND gate (MU1) and whose zero-state output (AO) is connected to the other input of the AND gate (UG1), while the other inputs of the multiple AND gate (MU1) are fed with the horizontal-deflection pulses (HA). The output pulses of the AND gate (UG1) are divided by a frequency divider (FT) and then counted in synchronism with the field frequency by a first presettable up-counter (VV1) which is preset by a second programmable read-only memory (PROM2) in which a digital word corresponding to the deflection current at the top or bottom of the image is stored. The pulses of another clock generator (TG1) are counted by a second presettable down-counter (RZ2) and a second presettable down-counter (VV2) after passing through one of the input-output paths of a second AND gate (UG2) and a third AND gate (UG3), respectively. The counts of the first presettable up-counter (VV1) preset the second presettable down-counter (RZ2) and the second presettable up-counter (VV2) via the first input-output paths of a second multiple AND gate (MU2) and a third multiple AND gate (MU3), respectively. The horizontal-deflection pulses (HA) are applied to the second inputs of the second and third multiple AND gates (MU2, MU3), whose third inputs are connected, via an inverter (IV) and directly, respectively, to the output (Am) of the first presettable up-counter (VV1) for the most significant bit. The count outputs of the second presettable down- and up-counters (RZ2, VV2) are respectively connected via first and second multiple OR gates (MO1, MO2) to the drive-signal outputs (A', A") for one and the other half of the image, which outputs are also coupled to the other inputs of the second AND gate (UG2) and the third AND gate (UG3), respectively.

A correction circuit is used with a horizontal deflection circuit, for the correction of an image distortion. The correction circuit comprises a line memory for sequentially fetching and storing one-field digital image data. The digital image data read out of the line memory is supplied to a D/A conversion circuit. This D/A conversion circuit converts the digital image data into an analog signal used for making a beam scan rate constant on the entire screen of a CRT. The data transfer rate used in both the line memory and the D/A conversion circuit is varied, with a clock supply rate adjusted by a frequency modulation circuit and an A/D conversion circuit on the basis of clock rate data.

A sweep generator for producing a circular raster of curved scanning lines on the target surface of a video camera is disclosed. Each curved trace follows a substantially circular path through a scanning angle of 360.degree.. The circular raster is generated by horizontal and vertical scanning signals which are synchronized with the horizontal line frequency of a video receiver. The horizontal scanning signal is characterized by a constant amplitude component followed by a sine wave component, and the vertical scanning signal is characterized by a composite waveform including a constant amplitude component followed by a sine wave component which is shifted 90.degree. in phase with respect to the sine wave of the horizontal scanning signal. The constant amplitude components of each composite waveform are synchronized with the horizontal blanking pulse which occurs during horizontal retrace of the scanning beam in the receiver, and the phase shifted sine waves are synchronized with the forward trace of each horizontal line in the receiver. This produces a one-to-one correspondence of each circular trace in the video camera with each horizontal forward trace in the receiver. The composite scanning signals are amplitude modulated by a sawtooth signal which is synchronized with the receiver field frequency, thereby producing a circular raster of concentric scanning lines. According to a preferred embodiment, each composite waveform is produced by a read only memory (ROM) which is synchronously cycled at the line frequency while driving a digital-to-analog converter. The modulating signal is generated by a sawtooth oscillator which is synchronized with the receiver field frequency.

In a video display operable at multiple horizontal scanning frequencies, a synchronized high voltage generator is substantially undisturbed during synchronizing source selection or interruption. The generator comprises a controlled oscillator generating a drive signal. A source of pulses synchronizes the controlled oscillator and has a plurality of scanning frequencies. A high voltage generator is coupled to the drive signal and generates a display energizing supply. The scanning frequencies occur in two frequency bands, and when synchronized the oscillator generates the drive signal having a frequency only in a higher frequency band of the two frequency bands. In a further inventive arrangement a high voltage generator for a video display is operable at a plurality of horizontal scanning frequencies and is controlled such that the high voltage supply remains substantially constant during an interruption of horizontal scanning pulses from the source.