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Semiconductor structure
   
Document Number
US Patent 4178195
Issued Date
December 11, 1979
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Abstract
A technique for fabricating a semiconductor heterostructure by growth of a ternary semiconductor on a binary semiconductor substrate from a melt of the ternary semiconductor containing less than saturation of at least one common ingredient of both the binary and ternary semiconductors wherein in a single temperature step the binary semiconductor substrate is etched, a p-n junction with specific device characteristics is produced in the binary semiconductor substrate by diffusion of a dopant from the melt and a region of the ternary semiconductor of precise conductivity type and thickness is grown by virtue of a change in the melt characteristics when the etched binary semiconductor enters the melt.
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Semiconductor structure - US Patent 4178195 Drawing
Drawing from US Patent 4178195
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Number of Claims:
10
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Published
December 11, 1979
Application Number
05/918,114
Filed
June 22, 1978
US Classification
438/89   136/262 257/184 257/437 257/459 257/E21.117 438/498 438/955
Int'l Classification
H01L   21/02   (20060101)   H01L   21/208   (20060101)   H01L   31/06   (20060101)   H01L   31/068   (20060101)  
Examiner
Parent Case
This is a divisional application of application No. Ser. No. 744,012 filed Nov. 22, 1976 now U.S. Pat. No. 4,122,476.
USPTO Field of Search
148/171   148/172   148/187   29/572   357/16   136/89SG  
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