A memory interface system employs a communications protocol to distinguish between command signals, address signals and data signals appearing on the same bus lines. Each memory coupled to the bus lines detects the change between a default state on the bus lines and a command signal. A detector within each memory determines from the received command signal the type of memory operation to be performed and prepares the memory for that operation. These operations may include reading or writing data within specified locations in the memory or reading or writing within the program counter associated with the memory. The detector is only responsive to received command signals when a predetermined state follows the default state.

For certain operations executed in a multiprocessor system, the processors communicate with one another by exchanging requests and acknowledgements. To improve performance, the invention proposes a method by which the operations which require sending of multiple requests proceed without taking into account the reception of the acknowledgements. The total number of requests required is calculated and the number of acknowledgements received is counted. The end of the operation is conditioned by the equality of these two numbers. The invention also relates to a system for employing the method, and to the application of the method to dispatching.

A system for sharing several memory modules by several processors on a common bus uses a protocol in which, after a processor gains access to a memory module read or write data is transferred on the bus within a preset number of system clock periods. After priority is established by polling, the processor sends memory address on the common bus. For each operation several idle system clock periods are provided before data is returned from the memory to permit the memory to retrieve the data. Meanwhile, the protocol interleaves requests for access to other memory modules from other processors thereby increasing the throughput of the system.

Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock domain. A second pulse converter receives the synchronization signal in the second clock domain from the first pulse converter and converts the synchronization signal into an acknowledgment signal in the first clock domain. The pulse converters cooperate thus to perform a self-acknowledging handshake that synchronizes writes and reads to and from a FIFO memory, thereby effectuating the transfer of data across two clock domains.

Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a system bus, lower priority users requesting access may be allowed selective and limited access to the system bus during those times in which a higher priority user is in either an idle or halt state or is engaged in utilizing another bus, such as an input/output bus or resident bus.