An operational amplifier wherein each of the active elements is comprised of complimentary coupled pairs of insulated gate type field effect transistors is provided. A first active stage and a second active stage are coupled together to perform a predetermined transfer function. Each active element in the first and second stages are insulated gate type field effect transistors that are coupled in complementary pairs with the first stage and second stage being coupled to define mirror pairs.
A voltage amplification circuit is provided which is capable of faithfully amplifying an input signal even in an inverting amplifier placed in a second stage being DC-coupled to an inverting amplifier placed in a first stage. By DC-coupling the inverting amplifiers and by setting an amplifying operation starting input voltage in the inverting amplifier placed in the first stage to be lower than that in the inverting amplifier placed in the second stage, the voltage amplification circuit that can provide a large amplification factor is realized. By configuring so that a circuit to set a clamping voltage has substantially the same configurations as a circuit to set an amplifying operation starting input voltage in the inverting amplifier placed in the second stage, the voltage amplification circuit is obtained that can follow variations in parameters on manufacturing and provide a wide operating margin and operate in a stable manner even though variations in parameters on manufacturing or variations in a source voltage occur.
A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.
A complementary field-effect transistor amplifier includes first, second, and third FET inverter amplifiers. Input signals are applied to input connections of the first and third inverter amplifiers and the output connections thereof respectively connect to first and second nodes. The first node connects to the input connection of the second inverter amplifier, the output connection of which amplifier connects to the second node where the input signals are combined. A fourth inverter amplifier includes a degenerative feedback connection and has its output connected for providing a load at the first node. Signals responsive to the combination of the first and second input signals can be further amplified by a fifth inverter amplifier and supplied therefrom to an output terminal.
An amplifier circuit for a speaker 12. The circuit includes an operational amplifier 16 connected to a supply rail 24 and a supply rail 26 through a regulator 28 and a regulator 30. The circuit is characterized by a P channel MOS-FET 32 having a source 34 connected to the rail 24 and a drain 36 connected to the speaker 12 and a gate 38, and an N channel MOS-FET 40 having a source 42 connected to the rail 26 and a drain 44 connected to the speaker 12 and a gate 46. A NPN stage 48 is responsive to the output 56 of the amplifier 16 for establishing a voltage differential between the gate 38 of the MOS-FET 32 and the rail 24 to drive the MOS-FET 32 into conduction. A PNP stage 50 is responsive to the output 56 of the amplifier 16 for establishing a voltage differential between the gate 46 of the MOS-FET 40 and the rail 26 to drive the MOS-FET 40 into conduction. The stages 48, 50 are connected to ground 52. A feedback circuit 94 interconnects the drain 36 of the MOS-FET 32 and the ground 52 side of the stage 48, and a feedback circuit 96 interconnects the drain 44 of the MOS-FET 40 and the ground 52 side of the stage 50. A feedback circuit 98 interconnects the speaker 12 and the amplifier 16 for returning a portion of the output voltage to the amplifier 16 to cause the output signal to track the signal at the input to the amplifier 16. A PNP transistor 68 has its base 72 connected to the source 34 of the MOS-FET 32 and its emitter 70 connected to the rail 24 and its collector 76 connected to the output 12, and an NPN transistor 82 has its base 84 connected to the source 42 of the MOS-FET 40 and its emitter 87 connected to the rail 24 and its collector 90 connected to the output 12.
The invention concerns differential amplifiers for computer disc drives, implemented in Metal Oxide Semiconductor (MOS) technology. The amplifiers are of the controllable-gain type. Gain is controlled by adjusting the channel current which passes through the differential Field-Effect Transistors (FETs) of the amplifier. The channel current can be viewed as having a constant component, to which is added an adjustment component. The adjustment component does not pass through the active loads of the differential amplifier, thereby allowing a larger change in gain to be attained.
