A gate turn-off thyristor comprises a semiconductor wafer (8) structured by an N-base layer (8c), a P-base layer (8b) adjacent to one side of the N-base layer (8c), an N-emitter layer 8d adjacent to the other side of the N-base layer (8c), and a plurality of N-emitter regions (8a) formed on the outer surface of the P-base layer (8b) excluding a region serving as a gate region and further comprises a first electrode (9) on the outer surface of the P-emitter layer (8d), second electrodes (5) on the outer surfaces of the N-emitter regions (8a), a gate electrode (4) on the outer surface of the gate region and a lead-out point (7) for the gate electrode, and the above described gate turn-off thyristor is characterized in that the semiconductor wafer (8) includes a plurality of areas (3A and 3B) having different carrier life times and that the life time is the longest in the first area (3A) where the gate lead-out point (7) is positioned, while the life time is shorter in the area (3B) farther from the gate lead-out point (7).

In a photothyristor provided with a cathode, a gate and an anode, the impurity densities of gate (base) portions 20 and 21 are made unequal to each other. The minority carriers are stored in the high impurity density regions 20, the majority carriers are permitted to readily pass through the low impurity density regions 21, and the high and low impurity density regions are electrically coupled together. This thyristor is extremely high in sensitivity and high-speed in operation.

One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions. The localized lifetime killing portion may comprise a plurality of laterally confined and laterally spaced apart lifetime killing regions. Another device may include one or more PN junctions.