A time counting control system comprises: a timing signal generator for generating at least a read-in clock signal on the basis of a reference clock signal outputted from a reference clock signal oscillator; a microprogram control unit including an address register which is controlled by the read-in clock signal outputted from the timing signal generator, an address section which decodes the contents of the address register and energizes address lines related to a plurality of processing steps, and a microprogram storing section which simultaneously outputs microprogrammed instructions and the address of the instruction to be succeedingly executed; and a count/operation unit which performs a counting operation under the control by instructions successively outputted from the microprogram storing section of the program control unit, includes an arithmetic device and a register connected to said arithmetic means to store counting information and is so controlled as to perform a counting operation each time the microprogram control unit processes the plurality of processing steps.
A time duration is measured precisely and with high resolution by making three time measurements as shown in FIG. 5. The time difference t.sub.A between the leading edge of a start signal and the next following leading edge of a constant frequency time base signal is measured. The number "n" of the following leading edges is then counted including the leading edge of the time base signal following a stop signal. The number n is multiplied by the period T.sub.Q of the time signal. The time difference t.sub.E between the leading edge of the stop signal and the next following leading edge of the time base signal is measured. The real time difference .DELTA.t is then calculated as follows .DELTA.t=t.sub.A +n.multidot.T.sub.Q -t.sub.E. A three part real time measurement is performed to correct the calculated result for drift and aging. Calibration measurements are made and the respective calibration factors are used in calculating the final results. The respective circuit arrangement includes a start channel, a stop channel, and the corresponding supporting circuits.
A measuring apparatus for measuring the time of execution of instructions or the number of cycles that addresses are within a selected address range of a memory. The measurement includes a measurement of any common subroutines that have been called by the instructions within the selected range. The measuring apparatus includes range circuitry connected to the address bus of the memory that detects instruction addresses within the selected range and instruction addresses within a common range having the common subroutines. The measuring apparatus further includes link logic for controlling a counter to both measure the instructions within the selected range and measure instructions within the common range when they immediately follow the selected range on the address bus. In the preferred embodiment, the memory is organized in ranges so that the first range begins at the first memory location in the memory and the last range ends at the last memory location in the memory. Any one of the ranges can be designated as a common range. The counter circuitry includes a plurality of counters, one associated with each of the ranges. Each counter can measure instruction addresses within its associated range and instruction addresses within a common range that immediately follow its associated range.
A system for measuring program execution time compares all addresses occurring on a memory bus to an upper limit number and a lower limit number to produce a signal which indicates if each address occurring on the memory bus is within a range represented by the upper limit number and the lower limit number. The signal is utilized to either enable incrementing of a counter at a predetermined rate or to increment the counter once for every new address occurring on the memory bus within the range. The contents of the counter represent either the accumulated time of execution of instructions having addresses within the range or the number of instructions executed having addresses within the range. The system includes a display for displaying the contents of the counter.
A clock integrated circuit comprises an oscillator circuit for producing a basic frequency signal, a frequency divider for frequency dividing the basic frequency signal to a predetermined frequency, a time measuring circuit for counting output pulses from the frequency divider to produce time data consisting of 1-second, 10-seconds, 1-minute, 10-minutes, 1-hour and 10-hours digits or a combination of some of these digits and a display driver circuit for displaying the time data on an external display means. Further, it comprises a digit selection circuit which outputs the afore-said time data such that the time data can be directly coupled to a central processing element.
For one of memory divisions that is selected at a time as a selected division N(m) in a memory for use in putting a sound processing device in operation of generating a three-dimensional image of an acoustic field, a difference signal is produced to represent a clock count minus a delay count n(m) specific to the selected division and to have more and less significant bits. For use as an address signal supplied to the memory, a part of the more significant bits is changed to a like part of a memory space address specific to the selected division. As usual, the less significant bits are used to indicate read aR(i(m)) and write W(i(m)) pointers which are spaced in the selected division by the delay count. The part may be specified to be wide and narrow when the selected division is narrow and wide. Alternatively, the part may have a predetermined bit width.
