A highly reliable electrooptical device comprises a pair of electrode plates facing each other with a space and sealed along their periphery by a sealing material to form a cell and an electrooptical material sealed in the cell. The device is characterized in that a protective layer of an electrically conductive material comprising electrically conductive particles and a binder is coated on each lead terminal extending outside the sealing material and the protective layer is partially embedded in the sealing material.

A liquid crystal device for direct display of analog information in images and patterns includes a layer of liquid crystal material sandwiched between a front and a back transparent plate. Transparent conducting films are applied to selected portions of the sides of both front and back transparent plates adjacent to the liquid material. A resistor network is provided electrically continuous with at least one of the transparent conducting films for impressing a voltage gradient transversely across the transparent conducting films so as to permit the selective, incremental reorientation of the liquid crystal material into the desired images and patterns.

A matrix addressable liquid crystal display includes a thin film circuit supported on a substrate having a plurality of parallel bit lines. A plurality of individual pixel circuits each include a two terminal bi-directional gate device which is formed from at least one thin film layer with one gate device terminal connected with the associated bit line. A terminal plate is connected in circuit with the other terminal of the gate device. A transparent cover plate is spaced above the thin film circuit with a transparent conductor structure on the underside of the cover plate. The space beneath the cover plate is filled with a liquid crystal display material to form individual display pixel circuits at the terminal plates. A plurality of parallel word lines are arranged orthogonally to, and insulated from, the bit lines. The word lines are connected in circuit with the individual display pixel circuits at the respective cross-overs with the bit lines. The pixel circuits are each operable to change the state of the associated portion of the liquid crystal display material in response to the concurrent application of voltage pulses of opposite polarities to the associated word and bit lines.

An optical modulation device suited for gradational display, includes a first conductor film electrically connected to a first electrode and a second electrode, and a second conductor film disposed opposite to the first conductor film, an optical modulation material disposed between the first and second conductor films; and driving means for (a) setting the first electrode at a first reference potential and supplying the second electrode with a first voltage of one polarity relative to the first reference potential to furnish the first conductor film with a first potential gradient; (b) supplying the second conductor film with a first voltage of the other polarity relative to the first reference potential in phase with the first voltage of one polarity; (c) setting the second electrode at a second reference potential and supplying the first electrode with a second voltage of the other polarity relative to the second reference potential to furnish the first conductor film with a second potential gradient; (d) supplying the second conductor film with a second voltage of one polarity relative to the second reference potential in phase with the second voltage of the other polarity; and (e) setting the second voltage of one (or the other) polarity to satisfy a compliment relationship with the first voltage of the other (or one) polarity.

The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. Furthermore, reference voltages are provided to decoding circuits by using distributed resistors. The decoding circuits utilize a cell layout that allows data to bused into the cell through polysilicon that also operates as the gate of the decode input transistors. The decode input transistors are arranged in strands of abutting transistors which may be connected in series or in parallel. Moreover, the decode cell input transistors may all be of the same conductivity type.