A first in-first out buffer memory coupled to a system bus receives all information transferred over the bus. Logic associated with the buffer memory tests if the information received is intended to update main memory or is in response to a cache request. The information is written into cache if the main memory address location is stored in a cache directory. The information received in response to a cache request is stored in a cache data buffer. Other information is discarded.
A bus control system includes a handshake control circuit connected to receive an information transfer request signal from a data bus and to generate an information receipt acknowledge signal. The handshake control circuit operates to control a handshake between the information transfer request signal and the information receipt acknowledge signal. A first in-first out type memory is coupled to the data bus and is controlled by the handshake control circuit so as to receive information from the data bus and to output information to the data bus. In addition, the memory outputs an empty signal when the memory is empty, and the empty signal is supplied to the handshake control circuit. A counter is provided to be preset with an information transfer number and coupled to receive the information receipt acknowledge signal generated by the handshake control circuit so as to count the number of the information transfers executed and to generate a transfer completion ready signal when the information transfers of the number less than the preset number of the information transfer by one have been executed. Furthermore, an information receipt acknowledge hold control circuit is coupled to receive the transfer completion ready signal. The information receipt acknowledge hold control circuit operates to control the handshake control circuit, after the transfer completion ready signal is activated, so as to cause the handshake control circuit to hold the information receipt acknowledge signal in an active condition after the information receipt acknowledge signal in correspondence to a last information transfer is activated and until the empty signal is activated to indicate the emptiness of the memory.
A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority operation which will give priority to invalidation cycles in the cache over the priority of the processor's cache access. When the FIFO queue indicates that it is almost empty, then the priority of the cache access by the processor is re-established as it was in normal conditions. The system operates concurrently in a self-regulating manner to load and unload addresses into the FIFO queue while also giving priority to flushing out the queue with invalidation cycles when preset upper limits are reached.
A cache store is provided in conjunction with a main store. Each location of the cache has a changed bit. A list is maintained of the addresses of those locations in the cache store which have been modified. When the list becomes full, the entry at the head of the list is read out and the corresponding data item is transferred from the cache to the main store. Thus, there are never more than a limited number of items in the cache awaiting transfer. To clear the cache of all modified items, each entry in the list is read out in turn and the corresponding items are transferred to the main store. The system reduces the amount of traffic between the cache and the main store and hence improves efficiency.
A memory system includes a main memory and a memory controller. The main memory includes at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of the FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst, and the timing resolution of the memory is enhanced regardless of the bus clock frequency. During burst transactions, the channels can run in an alternating fashion. During reads, the data is error-checked before being output to the system bus. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.
A store buffer apparatus connected to a CPU and a main storage unit includes a first buffer for holding a pair of store address and store data in the main storage unit supplied from an operation execution unit of the CPU, a first latch connected to the first buffer means for holding the store address, a second latch connected to the first latch for holding an output of the first latch, a judgment device for comparing an output read out from the address array with an output of the second latch to thereby judge whether the cache hit check for the store address is successful or not and a second buffer for holding the pair of store data and store address having successful cache hit check judged by the judgment device. Occurrence of the state that the store buffer is full is reduced. Two data stored in the second buffer can possess a format into which the two data can be merged.
