In a display managing arrangement comprising a display memory and a display memory controller for accessing the display memory to display a selected area of an image datum with the selected area scrolled on the image datum or otherwise subjected to management, the display memory is divided into memory blocks arranged as an N-row M-column matrix. Each memory block is for use as a unit of the management and is divisible into memory elements arranged as an n-row m-column matrix. When the memory elements of the display memory are assigned with serial memory element addresses along each row of the memory elements of the display memory and then along a next column-wise downward row, the memory controller may access the memory elements of selected ones of the memory blocks in block parallel by specifying the serial memory element addresses for each memory block on the one hand from a least memory element address in the memory block under consideration consecutively to the serial memory element address which is equal to the least memory element address plus the number m less one. On the other hand, the serial memory element addresses are specified discretely along one of the m columns by adding products of a step value mM and multipliers variable from zero to the number n less one to one of the serial memory element addresses that is congruent with the least memory element address modulo the step value. On storing the selected area in the display memory, the image datum may likewise be accessed.

An apparatus and method for scrolling windows of both graphic and graphic encoded text information on a raster scan display. The apparatus includes a processor which references a program store, and a video refresh buffer, the buffer containing graphic and graphic encoded text data in a pixel format adapted for directly refreshing the display. The processor is operated under control of the program store and responsive to information specifying the pixel locations of opposite corners of a window to be scrolled and the number of rows to be scrolled for calculating the size and location in the display refresh buffer of the window to be scrolled, and for moving the number of rows to be scrolled from source locations to destination locations within the window in the display refresh buffer.

A memory control unit for a computer has the function of extracting or synthesizing only a necessary portion from or to two-dimensional image scan data, in addition to a conventional main memory function. It comprises an address controller for calculating an address of data to be transferred based on source and destination start addresses A.sub.1 and A.sub.2 of the two-dimensional image scan data, a lateral length W.sub.1 and a longitudinal length of the necessary portion, and lengths I.sub.1 and I.sub.2 of unnecessary portion, and a controller for controlling memory read/write operation.

This video graphics raster display system effectively facilitates panning over an image that is arbitrarily larger than the image memory from which the display is generated. To accomplish this, the image memory is addressable "toroidally", i.e., in modulo or wraparound fashion. Thus, if a memory address boundary is reached during a raster readout, the readout continues without interruption from the opposite boundary. The image memory is slightly larger than would be required to store only the image currently being displayed. The excess memory area includes a border area, surrounding the current readout area, which contains image data that forms a continuation of the image currently being read out and displayed. This allows immediate panning into the border area. Further, the excess memory area includes a "rewrite area" on the other side of the border zone from the current readout area into which new, image continuation data may be entered while panning takes place. Appropriate circuitry facilitates new data entry to the rewrite area and controls the panning rate to ensure that the displayed image will not reach the rewrite area until after the new data has been entered.

The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. At the same time those signals are used to refresh the memory. During the alternate cycles (between refresh cycles) there may be a burst of signals from the signal path circuitry chip to write information into the bit map memory at some new address to effect scrolling. Instead of performing scrolling in the alternate cycles, information may be erased from a region. In the alternative there may be a burst of signals from an information source transmitted to the bit map memory to effect updating (i.e. writing new data information into the memory). The foregoing arrangement permits the entire bit map memory to be rewritten during the period required for one vertical scan of the video display device which in turn enables the system to provide rapid smooth scrolling and continued sequential addressing of the memory.