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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for electrooptically
sensing transmitting and recording picture patterns, as for example, in a
facsimile system wherein the picture pattern is scanned in a step-by-step
manner with a plurality of lines being simultaneously scanned with a
multihead scanning device and wherein the output information from the
scanning head is converted from parallel information into series
information.
2. Description of the Prior Art
German Patent published application No. 2,231,650 describes an arrangement
relative to its FIG. 2 which illustrates a sensing device with several
electro-optical converters arranged in a row which sense a scene which is
to be observed in several parallel lines. Parallel sensing is used in this
patent publication to combine the signals of adjacent channels so as to
improve the modulation-transfer function transverse to the sensing
direction. In military operations this will result in individual objects
being better recognized at greater distances.
German published patent application No. 2,351,986 describes a circuit
arrangement for a recording device including a discrete switch with a
plurality of electro-optical converter elements which uses a special
circuit for improving the picture information which is being sensed.
The magazine entitled "Electronik-Information", Volume 9 of Sept. 9, 1973
at pages 50-56 describes a "A Self-Sensing PhotoDiode Line" written by
Heinz Friedberg. The individual diodes in this article are connected to a
shift register which during the sensing process supplies a succession of
picture signals at its output which have been sensed by the individual
diodes in accordance with the picture dots one after the other. Such an
arrangement is well suited for electro-optically sensing of patterns.
The following German published patent applications and art serve as
background for the present invention:
DT-OS No. 2,231,650
DT-OS No. 2,351,986
DT-OS No. 2,219,442
DT-OS No. 1,903,964
DT-OS No. 2,354,520
DT-OS No. 1,762,090
DT-OS No. 1,908,834
DT-Auslegeschrift No. 2,034,350
U.S. Letters Pat. No. 3,814,846
"Electronic Information", Sept. 9, 1973, 5th Volume, Pages 50-56
SUMMARY OF THE INVENTION
If a sensing device having a sensing head with a plurality of
electro-optical elements is moved back and forth over a pattern as, for
example, in a facsimile system, a succession of picture signals will
appear as sensing signals which relate to different lines one after the
other. Since, however, the transmission of the picture signals in the
facsimile system is effected such that only line sequence signals are
transmitted and such signals are recorded line by line and image dot by
image dot at the recording site, the signals obtained by multiple head
scanning arrangements are not suited for this purpose. The reason for line
sequence transmission or sending of the picture signals is because there
are world-wide standards requiring that all recording devices which are
connected to a transmitter may operate compatible with each other. This
requires that the sensing devices being used match the patterns exactly
line by line with an individual photo-electric sensing arrangement which
will automatically assure and provide a line sequence signal. Since,
however, only one line is sensed at a time such a sensing system is very
slow in its sensing speed which also means that it requires a substantial
length of time to transmit a picture between a transmitter and receiving
station.
It is very desirable, however, to transmit pictures in shorter times and it
is, therefore, an object of the present invention to reduce the time
required for sensing a picture to be transmitted and recording such
picture at a receiving site.
The present invention has an object to provide a simple and quick method
and apparatus for sensing, transmitting and recording picture patterns
which can be used with commonly available transmission techniques for
facsimile transmission.
Other objects, features and advantages of the invention will be readily
apparent from the following description of certain preferred embodiments
thereof taken in conjunction with the accompanying drawings although
variations and modifications may be effected without departing from the
spirit and scope of the novel concepts of the disclosure, and in which:
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view illustrating a plural scanning head;
FIG. 2 is a plan view of a picture being scanned to show the incremental
elements and the sensing raster;
FIG. 3 is a block diagram illustrating a circuit arrangement for the
invention;
FIG. 3a is an example for the switch 13 of FIG. 3,
FIG. 3b is a circuit diagram for the timing generator of FIG. 3;
FIGS. 4a, 4b and 4c illustrate the timing wave patterns for synchronizing
the circuit of FIG. 3;
FIG. 5 is a block diagram of a receiver of the invention;
FIG. 5a is a circuit diagram of the timing generator of FIG. 5;
FIGS. 6a, 6b and 6c illustrate timing waves for the receiver of FIG. 5;
FIG. 7 illustrates in block form a modified memory device;
FIG. 7a is an example for the modified memory device of FIG. 7; and
FIG. 7b is a circuit diagram for the timing generator of FIG. 7.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 illustrates a flat bed sensor so as to simplify and clarify the
sensing principle of the present invention.
A pattern to be scanned 1 is scanned by a sensing head 2 which includes a
plurality of electro-optical converters such as photodiodes 4 mounted
side-to-side in the head 2 and which are scanned across the picture 1
between the dashed lines 3 such that each time the head 2 passes across
the sheet 1 an area between adjacent dashed lines 3 is scanned. For
clarity, the device for driving and moving the sensing head 2 is not
illustrated. Such drive means are well known in the art. Because the head
2 has a plurality of electro-optical converters or photo-diodes 4 the head
2 may be scanned back and forth across the paper much slower than a head
which carries a single photo-electric converter since a larger area is
scanned by the head of the invention than with a single electro-optical
converter of the prior art. After the head 2 scans across the area defined
by the dashed lines 3 the picture 1 is advanced by a motor 8 which drives
a pulley 7 that drives the rollers 5 and 6 to advance the picture in a
step fashion in the direction of the arrow 9. The head 2 continues to scan
after each advancement of the picture 1 until the complete area of the
picture has been scanned.
FIG. 2 is a plan view of the picture to be scanned and illustrates the
picture 1 and the sensing head 2 with its plurality of electro-optical
elements 4 which is moved in the direction of the arrow 10 across the
picture 1 and the picture is advanced in the direction of the arrow 9 as
in FIG. 1.
The picture 1 is subdivided into 1, 2, 3, 4 . . . i . . . n columns and
into 1, 2, 3 . . . k . . . m lines. In the example of FIG. 2, the sensing
head has either electro-optical sensors 4 and, thus, the sensing head
scans a total of eight lines simultaneously. Thus, one picture dot which
is to be sensed is defined by the intersection of two columns and two
lines which define four intersections. The row 4 of the plural photo-diode
head is interrogated in the direction of arrow 11 or in the opposite
direction 9 with a timing which is a multiple faster than the advancing
movement of the sensing head so that the picture signals of a column will
appear one after another at the output of the sensing head which, however,
belong to different lines in succession.
FIG. 3 is a block diagram illustrating how the signals obtained by the
multiple electro-optical sensing head 2 are converted into line sequence
signals. The sensing head 2 may, for instance, have k diodes as is
described in the magazine "Electronik Information", Sept. 9, 1973, 5th
Volume, at pages 50-56. Such picture signals are arranged in accordance
with the columns shown in FIG. 2, and are supplied to a switch 13 through
a line 12 from where they are distributed to distribution switches 13a or
13b which are controlled by the counters 14a and 14b, respectively.
Both of the counters 14a and 14b as well as the sensing head 2 receive
outputs from a timing generator 15 which is described in detail in FIG. 3b
so as to cause the sensing head to move and to drive the counters 14a and
14b. The timing impulses from the generator 15 via line 16 are called the
synchronizing signals. The synchronizing signals determine the speed at
which the output picture signals are obtained one picture signal after
another from a shift register. The shift register receives the output of a
single photo diode and produces a line of information. The information
from the sensing head 2 is separated by the distribution switches 13a and
13b into information corresponding to individual lines from the picture
and are then supplied to a plurality of line shift registers S.sub.1
through S.sub.2k. The number of shift registers corresponds to two times
the number of individual photo diodes in the scanning head 2. The shift
register to be used may be type MM 5058 from National Semiconductor.
A detailed description of the switch 13 is provided in FIG. 3a. The line 12
is connected to two AND-gates 131 and 132. The second input of the
AND-gate 132 is connected to a circuit point C13 which receives switching
pulses from the pulse generator 15. The second input of the AND-gate 131
is connected to point C13 via an inverter 133. The AND-gates 131 and 132
become alternatively conductive in response to the signal originating from
the pulse generator 15, i.e. the signals from the scanning device 2 are
alternately passed on to the distributor circuits 13a and 13b. These
distributor switches 13a and 13b may be switches of the type SN 74 LS 138
by Texas Instruments, and the counters 14a and 14b may be of the type SN
74163 by Texas Instruments. Multi-level counters are obtained when
utilizing the generally known technique of cascading.
The output of the timing generator 15 is supplied by leads 17, through 22
to the shift registers S.sub.1 through S.sub.2k as shown. At a particular
time, the picture signal arriving at line 12 will be processed to the
first shift register S.sub.1 under control of the counter 14a through the
distribution switch 13a and line 23. During the next sensing sequence, the
distribution switch 13a switches the picture signal arriving at line 12
onto line 24 which will store this signal in the shift register S.sub.2
which corresponds to the second line. This process continues until the
last diode k of the diode line of the sensing head 2 has been interrogated
and the picture signal of the k diode will be stored in shift register
S.sub.k.
During the next sensing sequence, a shift inpulse is sent from the timing
generator 15 to the shift register S.sub.1 and simultaneously the counter
14a will have again switched the distribution switch 13a to line 23 and,
thus, the signal emitted by the first diode will be supplied to the shift
register S.sub.1 whose first stage will have been cleared by the shift
impulse. During the next impulse, the first position of the shift register
S.sub.2 is cleared and the switch 13a is connected to line 24 so that the
picture signal of the second diode is supplied to the shift register
S.sub.2. This process repeats until a complete line length has been
scanned by the sensing head 2 and the shift registers S.sub.1 and S.sub.k
are filled.
An end of line impulse causes switch 13 to change and moves it so that the
output of the sensing head supplied through line 12 is supplied to the
distributing switches 13b rather than to distributing switch 13a. The
distributing switches 13b are connected to the shift registers S.sub.k+1
through S.sub.2k. It is to be realized that the same number of shift
registers are connected to the distributing switch 13b as are connected to
the distributing switches 13a. After the pattern 1 has been shifted by the
motor 8 for a length corresponding to the distance between the dashed
lines 3 and the scanning head 2 has been returned to the first edge of the
paper, the sensing of a new line will commence. The first sensing impulse
switches the distribution switch 13b to the shift register S.sub.k+1 under
control of the counter 14b and it receives a first picture signal from the
first diode of the diode line. During the second sensing impulse, the
switch 13b will switch the output to the next shift register S.sub.k+2
which will obtain the picture signal from the second diode.
This process continues until the shift registers S.sub.k+1 through S.sub.2k
are filled and synchronizing signal will reach the timing inputs 21 and 22
which will clear the first stages for the following picture signals.
However when the new line multiple is sensed, the shift register S.sub.1 is
supplied the interrogation synchronizing signal by the timing generator
through line 17 and since it is already filled it will start reading out
its information to a multiplexer 30. Such multiplexers are available from
Texas Instruments, Type SN 74150. All of the shift registers S.sub.1
through S.sub.2k are connected to the multiplexer 30 which also receives
an input from a counter 31 which receives the synchronizing signal from
the timing generator 15. The counter 31 may be of the type SN 7493, SN
74393 or any other available counter of Texas Instruments. The line
synchronizing signal is composed of the successive line end signals and
can be produced in a simple manner during the sensing process by a contact
or a light barrier which is engaged when the sensing head 2 has reached
the end of a line. The multiplexer 30 processes the signals and supplies
them to a transmission line 32. If the shift register S.sub.1 is counted
until it is emptied, the multiplexer 30 controlled by the counter 31 will
shift the shift register S.sub.2 to the transmission line 32 and this
process will continue until the shift registers S.sub.1 through S.sub.k
have been emptied. The supplying of the information from the shift
registers S.sub.1 through S.sub.k through the multiplexer to the
transmission line 32 occurs while incoming signals from the sensing head 2
are supplied through the distributing switches 13b to the shift registers
S.sub.k+1 through S.sub.2k so one-half of the shift registers are
receiving information from the sensing head 2 while information is being
read from the other half of the shift registers which information was
stored during the previous scanning cycle. Thus, in the invention, the
output of the sensing head is supplied to a first group of shift registers
which equal the number of sensing elements in the head 2 during a first
time sequence after which the input from the sensing head is switched to a
second group of shift registers which also equal the number of sensing
elements in the sensing head and during such second period the information
stored in the first group of shift registers is furnished to the
multiplexer 30 and transmitted to a modem 32' which is arranged between
the multiplexer 30 and the transmission path.
Modems of this kind are used at the beginning and at the end of a
transmission path in facsimile and data transmission, and merely take care
of a constant data flow and an adjustment to the transmission speed. Such
modems are available and standardized. In the present case, for example, a
modem of the firm Codex, Type Codex 4800 can be utilized which transmits
with a constant bitrate of, for example, 4800 bit/sec. In order to achieve
a transmission with the aid of such a modem, an adjustment of the
transmission and receiver device to the transmission rate, i.e. to the
modem pulse, is required. This modem, in principle, has nothing to do with
the present invention, however, it is mentioned in order to completely
describe the transmission path.
FIG. 3b illustrates the pulse generator 15 of FIG. 3 more closely. The
example of FIG. 3b illustrates the case where K=8, i.e. 8 photo-elements
are combined in the scanning device. In accordance therewith 2.times.8
shift registers are also provided in FIG. 3. The scanning apparatus has a
pulse oscillator 420 providing the so-called machine pulse T.sub.A
illustrated in detail in the FIGS. 4a and 4c. This is the pulse which
causes the scanning to be carried out and from which the other pulses are
derived which are more closely described in the following. The pulse
frequency of this pulse may lie, for example, at about 250 kHz to 500 kHz.
A module of type K 1100 A, the crystal-oscillator from Motorola can be
utilized as the generator. This oscillator provides quartz-stabilized
pulses.
A different suitable phase generator, of course, can also be used.
An AND-gate 421 is connected at the outlet side of the generator 420, said
gate is controlled by a contact 423 or a light barrier signaling the line
begin or line end during the scanning. These impulses are led from the
position of the scanning device in a known manner at the respective line
begin or line end, and as many pulses are cut out of the pulse sequence
provided by the generator 420, referenced with T.sub.A in FIG. 4a, via the
AND-gate 421, as the length of a scanning line. In the present case, the
number of pulses is 1024, which is illustrated in FIG. 4a and FIG. 4c by
the pulse train C.sub.2 or by the path T.sub.p, respectively. This output
impulse row of the AND-gate 421 goes to two additional AND-gates 422 and
422' which, together with a flip-flop 424 represent a switch. The
flip-flop 424 may have been set to 0 before beginning the scanning by, for
example, a switch 425 present in the apparatus (general reset). The
flip-flop is set at the line begin by means of the line switch 423, i.e.
its Q-outlet may be one, its Q-outlet may be 0. The impulse row C.sub.2
reaches the AND-gate 422' with the through-connecting of the AND-gate 421,
said AND-gate 422' connects through and triggers the counter 426 which is
a 3-bit-binary counter. This counter was also previously set to 0 (general
reset) by means of the switch 425. The output of the AND-gate 422',
moreover, is connected with the impulse information input 1 of a 3 to
8-demultiplexer 427 which is triggered by the counter 426. With each pulse
coming from the AND-gate 422', the counter 426 transfers the multiplexer
427 to one of the outlets Q1 through Q8. The outlets Q1 through Q8 of the
demultiplexer 427 are connected with OR-gates T.sub.1 through T.sub.16,
whose outlets form the write pulse lines T.sub.S1, T.sub.S2 through
T.sub.S16, which represent the lines going from the pulse generator 15 to
the shift registers S.sub.1 through S.sub.2k (S.sub.1 through S.sub.16) in
FIG. 3.
In order to clarify the read-in process from the scanning device into the
write register, the pulse diagrams of FIG. 4a through FIG. 4c are used in
conjunction with the FIGS. 3 and 3b. As stated, a set of shift registers
S.sub.1 through S.sub.k should be loaded while the other set is read out,
and vice-versa. The alternating writing into the shift register is
accomplished with the switch 13 with the aid of the shift pulses C.sub.13
of FIG. 4a and FIG. 4c originating from the flip-flop 424 and the switch
423. The information at switch 13 reaches the distributor switches 13a and
13b which are multiplexers, which are controlled by the counters 14a and
14b. The counters receive their counter pulses via the outlets C.sub.14a
and C.sub.14b of the generator 15 originating from the AND-gates 422 and
423 of the circuit in FIG. 3b, and such pulses are illustrated as impulse
sequences in FIG. 4a. The individual pulses are drawn in FIG. 4c in an
enlarged scale.
FIG. 4c illustrates in the upper portion the write impulses T.sub.Sk+1
through T.sub.S2k for the case when the second block of shift registers is
being loaded. In that case the gate 422 is opened, the pulse sequence
C.sub.2 equals C.sub.14b which reach the counter 428 controlling the
distribution of the output impulses of gate 428 pulse sequence 14b, the
pulse lines T.sub.Sk+1 through T.sub.2Sk, i.e. T.sub.S9 through T.sub.S16,
whereby the information arriving via the output lines I.sub.k+1 through
I.sub.2k of the distributor switch 13b are distributed to the shift
registers S.sub.k+1 through S.sub.2k.
The registers S.sub.1 through S.sub.k are to be read out simultaneously.
The modem pulses T.sub.M originating from the modem 32, which are
illustrated in FIG. 4a and FIG. 4b are supplied to a 10-bit counter 431
which is connected with a multiple AND-gate 432 and gives out an impulse
after 10-bits, i.e. after 1024 impulses. The modem pulse occurs at a 4800
Hz rate corresponding with a bit-rate of 4800 bit/sec.
The modem pulse T.sub.M additionally reaches an AND-gate 433 connected at
the outlet side of the gate 432, and said AND-gate 433 triggers a 4
bit-binary counter 434 which triggers a 4 to 16 multiplexer 435. The
counters 431 and 434 may have been set to O before the scanning begin by a
general reset signal. If the modem starts the picture signal transmission
then the modem pulse T.sub.M begins and reaches the outlet Q.sub.1 of the
demultiplexer 435 and thus the OR-gate T.sub.1 via the information input
of the demultiplexer 435, and thus reaches as a write pulse the shift
register S.sub.1 which is connected to the modem 32 via the multiplexer 30
of FIG. 3. The multiplexer 30 is controlled by the counter 31, and is
again loaded by the pulse C.sub.31 which is at the inlet Q.sub.1, and
thus, the shift register S.sub.1 is connected to the modem.
If a line-length of the modem pulse occurs, i.e. gate 432 gives off an
output impulse, and the shift register S.sub.1 is empty, the AND-gate 432
is opened by means of the next modem pulse, the counter 434 increases by
one, the information input I of the demultiplexer is applied to the outlet
Q.sub.2, and a timing pulse appears on line C.sub.31 which applies the
Q.sub.2 input of the multiplexer 30 to the modem 32' via the counter 31.
Thus, the shift impulse series for the readout of the shift register
S.sub.2 passes out through the OR-gate T.sub.2, i.e. the shift register
S.sub.2 is emptied. This process goes on until the shift register S.sub.16
is empty.
However, the switch 13 has switched in the meantime, whereby again an
information input resulted from the scanner during the readout of the last
shift registers of the first shift registers, which was initially
described. The shift pulses for the readout, and the switch pulse for the
counters 434 and 31 are illustrated in FIG. 4b. Thus, the pulse C.sub.31
is a line-end pulse which is derived for switching the shift registers.
The following available components can be used for the individual
assemblies in the circuit of FIG. 5 or 5b, respectively:
Demultiplexer 33: Texas Instruments Ser. No. 74154
Counter 34: Texas Instruments Ser. No. 74163
Shift Registers S.sub.1 through S.sub.2k : National Semiconductor
Separators W1 through Wk: In each case one quarter of the module Ser. No.
74157 by Texas Instruments
FIG. 5 illustrates a receiver according to the principles of the invention
in which the line sequence picture signals arrive over a transmission path
which can then be recorded with a multiple parallel writing head that is
connected to the output of writing amplifiers V.sub.1 through V.sub.k. It
is to be realized, of course, the transmission of the signals between the
transmitting and receiving station need not be made by cable or wire lines
but could also be accomplished by radio transmission if desired.
The demultiplexer 33 receives the incoming signal over a modem 32' and is
controlled by a counter 34 which receives an input from the timing
generator 42. The demultiplexer 33 supplies the arriving picture signals
of the first line through conductor 35 to a first shift register S.sub.1
which is designed to receive the signals of a complete line. When the
register S.sub.1 is filled, the second register S.sub.2 receives the
output of the demultiplexer 33 through line 36 which is connected to the
input line 32 by the demultiplexer. This continues until all of the
registers S.sub.1 through S.sub.k are filled and there are twice as many
registers as there are parallel writing heads. It will be assumed in this
example that there are the same number of writing heads k as there are
diode sensing elements of the sensing head.
After the first set of line shift registers S.sub.1 through S.sub.k have
been filled, the output of the demultiplexer 33 is connected to the shift
registers S.sub.k+1 through S.sub.2k which are then filled line by line.
The timing sequence for advancing the shifting of the picture signals of
the shift registers are supplied from the timing generator 42 through
lines 43 through 49 into the timing inputs of the shift registers S. It is
advantageous if the timing base at which the picture signals arrive via
line 32 are used as the shift timing base. As the shift registers S.sub.+1
through S.sub.2k are being filled the shift registers S.sub.1 through
S.sub.k can be read out in parallel and this is effected by way of
switches W.sub.1 through W.sub.k each of which are respectively connected
to the shift registers and which supply the picture signals read out from
the registers to the writing amplifiers V.sub.1 through V.sub.k of the
multiple parallel writing heads through gates T.sub.1 ' through T.sub.k '.
The switch W.sub.1 has one of its inputs connected to the register S.sub.1
and its other input connected to the register S.sub.k+1. If the register
S.sub.k+1 is filled, the switch W.sub.1 connects the register S.sub.1 to
the gate T.sub.1 '. In the other situation the register S.sub.k+1 is
connected to the gate T.sub.1 while the register S.sub.1 is being filled.
In the same manner, the other shift registers are connected to the writing
head through switches W.sub.2 through W.sub.k so that the alternate
read-into and read-out of the picture signal into the shift registers is
accomplished. The switching of the switches from one set of shift
registers S.sub.1 through S.sub.k to the other set of shift registers
S.sub.k+1 through S.sub.2k is accomplished by line 51 which receives an
output of the timing generator 42 which supplies a switching impulse when
the two shift register groups S.sub.1 through S.sub.k and S.sub.k+1
through S.sub.2k are respectively being filled or emptied. The gates
T.sub.1 ' through 1K' assure that the exact beginning of the recordation
can be determined by way of the timing starting line 52 which is connected
to the output of the timing generator 42.
The pulse generator 42 is illustrated in more detail in FIG. 5a. A pulse
oscillator 520 is mounted in the receiver apparatus has the same purpose
and mode of operation as the generator 420 of FIG. 3b. The same module as
in FIG. 3b can be used. It provides the write pulse T.sub.S which triggers
the recording devices V.sub.1 through V.sub.k. A line switch 523 is
provided along with the pulse generator 520, and such line switch controls
a flip flop 524 and an AND-gate 521 as in FIG. 3b. Two AND-gates 522 and
522' are connected at the outlet side of the flip-flop 524, as in FIG. 3b.
These two AND-gates switch the shift pulses to the two shift register
blocks S.sub.1 through S.sub.8, or S.sub.9 through S.sub.16, respectively.
A positive voltage is applied to the flip-flop 524, which is set to 0 by
means of the switch 525 (general reset) before the beginning of the
transmission, by means of the line switch 523. Its Q-output has the value
of 0 and its Q-transverse outlet has the value of 1. As long as the gate
521 is open, i.e. during the length of a line multiple, the AND-gate 522
is also open. Its outlet pulse T.sub.S appears at the OR-gates T.sub.9
through T.sub.16. At the end of the first line multiple the switch 523
cuts off the positive voltage, and the flip-flop 524 is set by means of
the negative flank. The value of 1 is then at the Q-outlet, and the value
of 0 is at the Q-transverse outlet. These make the gate 522' open, i.e the
signals are switched from gate 522 to gate 522', and the pulses T.sub.S go
to the OR-gates T.sub.1 through T.sub.8.
Impulses C.sub.W furthermore reach alternatingly the separators W.sub.1
through W.sub.k. Also impulse row C.sub.T reaches the AND-gates T'.sub.1
through T'.sub.k with each switching of the flip-flop 524.
The control for the distribution of informations received from the line via
the modem 32" to the shift registers S.sub.1 through S.sub.2k is provided
in the upper portion of FIG. 5a. As soon as the picture transmission
starts, the modem 32" produces the modem pulse T.sub.M corresponding to
the pulse of the modem the the transmitter. The modem pulse goes to a
10-bit-binary counter 531 which has at its output a multiple-AND-gate 532
which also becomes opened in the case a 1 is present at the outputs of the
counter 531. This also occurs when the number of image points representing
a line length, is obtained. In the first line the modem pulse lies
directly above the information input I of the demultiplexer 535 at the
output Q.sub.1 of the demultiplexer. The pulse sequence goes to the shift
register S.sub.1 as shift pulse sequence T.sub.S1 via the output Q.sub.1
and the OR-gate T.sub.1. The demultiplexer 33 has a counter 34 as shown in
FIG. 5 and constructed exactly the same as the demultiplexer 535 and the
counter 534 of FIG. 5a. The information coming from the modem also goes to
the outlet Q.sub.1 of the demultiple | | |
