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Claims  |
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We claim:
1. An electrical appliance control system for controlling electrical
appliances within a building and comprising:
(a) a power main of the building;
(b) a plurality of power outlets of the main;
(c) a transmitter unit having:
(1) input means for entering any one of a plurality of addresses into the
transmitter unit;
(2) means for generating, synchronously with the mains voltage, a multibit
digital signal, comprising a multibit digital address signal representing
an entered address, the digital signal being modulated on a carrier the
frequency of which is a plurality of times greater than mains frequency,
so that the bits of the digital signal comprise predetermined numbers of
cycles of the carrier, the predetermined numbers depending upon the bit
values, and a period within each bit occurring near a zero crossing point
of the mains voltage; and
(3) output means for coupling the modulated digital signal onto the main;
and
(d) at least one slave unit for controlling the supply of power to
appliances and having:
(1) means for defining an address for that slave unit;
(2) a power input coupled to the main within the building;
(3) means for receiving from said power input said digital signal;
(4) means for recognizing the logical values of the bits of the received
digital signal by counting during said period the number of cycles of the
carrier and determining the value of the bit in dependence upon which of
two non-overlapping number ranges contains the counted number; and
(5) means for comparing the digital address signal received by the
receiving means with the address of the defining means and for rendering
the slave unit operable to effect an appliance power supply control
operation when correspondence is found between said address and the
digital address signal;
(e) at least one of the transmitter and slave unit being releasably coupled
to a power outlet of the main so as to be usable optionally at various
placed within the building.
2. A system as claimed in claim 1, wherein said input means of the
transmitter unit is also operable to enter a desired appliance power
supply control operation; and wherein said means for generating is further
operable for generating, as part of said multi-bit digital signal, a
digital operation signal representing the defined operation and for
supplying said digital operation signal to the output means for injection
onto the main; and
at least one slave unit comprising: means responsive to a received digital
operation signal, when the slave unit has been rendered operable by a
digital address signal, to effect an appliance power supply control
operation as defined by the digital operation signal.
3. A system as claimed in claim 2, wherein at least one slave unit has a
lighting dimmer control arrangement coupled to be controlled by the
responsive means in dependence upon a received digital operation signal,
and the input means of the transmitter includes means for entering desired
dimming and brightening operations for encoding in the digital operation
signals.
4. A system as claimed in claim 2, wherein the input means comprises a
keyboard for entering said appliance power supply control operation and
any one of said plurality of slave unit digital addresses.
5. A system as claimed in claim 4, wherein the input means comprises an
ultrasonic receiver by which data can be entered into the transmitter
unit.
6. A system as claimed in claim 2, wherein the transmitter unit comprises:
means for including in each digital signal a system code; and
each slave unit comprises:
means for defining a system code; and
means for comparing the defined system code with the system code in a
received digital signal and for responding to a correspondence between the
system codes as a condition for response of the slave unit to other data
in the received digital signal.
7. A system as claimed in claim 6, wherein the generating means comprises
means for producing each digital signal as a combination of data in its
logical true and logical inverse forms, and each slave unit comprises a
comparator for comparing the true and inverse forms and for enabling the
slave unit to respond only when correspondence between the true and
inverse forms is detected.
8. A system as claimed in claim 7, wherein the generating means is operable
to cause each digital address signal and a given range of the digital
operation signals to be transmitted onto the main at least twice.
9. A system as claimed in claim 7, wherein each slave unit comprises: an
address memory to store the acceptance of an address by the comparing
means to render the slave unit operable to effect an appliance power
supply control operation; and means for clearing the memory on the
condition that a subsequent digital operation signal has been received and
accepted.
10. A system as claimed in claim 9, wherein the clearing means is operable
to clear the memory when another address is detected following response to
said subsequent digital operation signal.
11. A system as claimed in claim 9, wherein at least one slave unit has a
power outlet for connection to an appliance having an operating switch and
sensing means for energising said power outlet on sensing at said power
outlet a condition indicative of the operation of the operating switch of
an appliance.
12. A system as claimed in claim 2, wherein the generating means comprises
means for producing each digital signal as a sequence of bits every other
one of which is followed in the sequence by its logical inverse, and each
slave unit has a comparator for comparing the alternate bits with the
intermediate bits to enable the slave unit to respond only when
correspondence is detected by said comparator.
13. A system as claimed in claim 12, wherein the generating means is
operable to precede each digital signal with a digital start code also
modulated on said carrier, and each slave unit has means for detecting
said start code to identify the beginning of the digital signals.
14. A system as claimed in claim 13, wherein the transmitter unit comprises
means for enabling each digital signal to be transmitted onto the main at
least twice.
15. A system as claimed in claim 2, wherein the transmitter unit comprises
a plug for plugging into one of said power outlets and a transformer
coupling the plug to the output means.
16. A system as claimed in claim 2, wherein each slave unit has a
transformer coupling the power input to the receiving means, and at least
one slave unit has a plug coupled to the power input for plugging the unit
into one of said power outlets.
17. A system as claimed in claim 2, wherein the transmitter unit is
operable to produce at least one digital operation signal in a form
constituting a general operation command, and a plurality of slave units
each comprising means responsive to detect and act on said general
operation command without prior response to a digital address signal.
18. A system as claimed in claim 2, wherein at least some slave units
comprise an address latch to store the receipt of the address of that
slave unit and means for resetting the latch when another address is
detected following response to one of said digital operation signals,
whereby a group of slave units can be addressed in sequence for control by
a single digital operation signal.
19. A system as claimed in claim 2, wherein at least one slave unit
comprises a power outlet, means for applying a test voltage to said outlet
and sensing means for energising said outlet with mains voltage on sensing
a given change in a parameter of said test voltage indicative of the
actuation of an operating switch of an appliance when connected to the
outlet.
20. A system as claimed in claim 12, wherein at least one slave unit
comprises a power outlet, means for applying a test voltage to said outlet
and sensing means for energising the outlet with mains voltage on sensing
a given phase change in said test voltage.
21. A system according to claim 7, wherein the generating means is operable
to produce the bits of the digital signals in respective time intervals
synchronized with the mains voltage, a bit of one logic value being
produced as a given number of cycles of the carrier in one of said time
intervals and a bit of a second logic value being produced as an absence
of cycles of the carrier in one of said time intervals.
22. A system as claimed in claim 21, wherein the recognizing means of each
slave unit has counting means for counting carrier cycles only within said
time intervals to identify the logic values.
23. A system as claimed in claim 22, wherein the generating means produces
each of said bits for a first time period within an interval and said
counting means is operable to count pulses in a second time period within
an interval, said second time period being shorter than and within the
first time period relative to mains voltage zero-crossing points.
24. A system as claimed in claim 2, wherein the bits are transmitted within
periods containing a zero-crossing point and each of a duration no greater
than one eighth of a half-cycle of mains voltage.
25. A system as claimed in claim 24, wherein the generating means repeats
each bit twice in one half-cycle of mains voltage, the transmitter unit
comprising a timer to time said repetitions to occur substantially
60.degree. and 120.degree. after the beginning of the half-cycle.
26. A transmitter comprising:
input means for entering data defining an address and an appliance
operation;
signal output means for connection to a power outlet socket of a domestic
power main; and
generating means coupled to the input and output means to produce, at the
output means and in synchronism with mains voltage, digital signals
defining said data comprising data bits modulated on a carrier having a
frequency a plurality of times greater than mains frequency so that bits
comprise predetermined numbers of cycles of the carrier, the predetermined
numbers depending upon the bit values, and the bits existing within time
periods containing a zero-crossing of the mains voltage and each period of
a duration no greater than one-eighth of a half-cycle of mains voltage.
27. A slave unit comprising:
electrical plug pins for plugging the unit into an outlet socket of a
domestic electrical power main;
means for connecting the power input of an electrical appliance to the
unit;
a current control device coupled between the pins and the connecting means
to control the energisation of the appliance;
means for defining an address for the unit; and
means responsive to a multibit digital signal arriving at the pins,
modulated on a carrier having a frequency a plurality of times greater
than mains frequency the responsive means including counting means for
counting the number of cycles of the carrier in periods which are short in
relation to a half-cycle of the mains voltage and which are near zero
crossing points of the mains voltage;
means for determining the values of the bits in dependence upon which of
two non-overlapping ranges contains the counted numbers for said periods;
and a comparator for comparing the address defined by the defining means
with one portion of the digital signal and for producing a signal to
control the current control device in dependence upon another portion of
the digital signal when correspondence is found between said address and
said one portion of the digital signal.
28. A slave unit comprising:
means for coupling the unit to a domestic power main;
means for connecting a lighting appliance to the unit;
a light intensity control device coupled between the coupling and
connecting means for controlling the brightness of a lighting appliance;
means for defining an address of the unit;
means responsive to a multibit digital signal arriving at the coupling
means, modulated on a carrier having a frequency a plurality of times
greater than mains frequency, the responsive means including counting
means for counting the number of cycles of the carrier in periods which
are short in relation to a half-cycle of the mains voltage and which are
near zero crossing points of the mains voltage, means for determining the
values of the bits in dependence upon which of two non-overlapping ranges
contains the counted numbers for said periods and a comparator for
comparing a first, address, portion of the digital signal with the defined
address and for operating the control device in dependence upon another,
control, portion of the digital signal arriving at the coupling means when
correspondence is found between the address and said first portion of the
digital signal.
29. A slave unit as claimed in claim 28, comprising:
means for counting the number of repetitions of one of a digital dimming
and brightening operation signal received and for controlling the extent
of operation of said lighting intensity control device in dependence upon
the number of repetitions counted.
30. A system as claimed in claim 3, wherein said generating means of the
transmitter is arranged to generate the digital operation signals
representing dimming and brightening operations repeatedly while said
dimming and brightening operations are being entered in the input means,
and the responsive means of said at least one slave unit comprises
counting means for counting the number of repetitions of a received
digital operation signal representing one of a dimming and a brightening
operation, and is arranged to control the extent of dimming and
brightening in dependence upon said number of repetitions counted.
31. A transmitter comprising:
input means for receiving data defining an address and an appliance
operation;
means coupled to the input means for generating, synchronously with the
mains voltage, multibit digital signals so that bits comprise
predetermined numbers of cycles of a carrier having a frequency a
plurality of times greater than mains frequency, the predetermined numbers
depending upon the bit values, a period within each bit occurring near a
zero crossing point of the mains voltage, and the digital signal defining
said address and said appliance operation; and
an electrical plug coupled to the generating means for plugging into a
power outlet socket of a domestic power main to inject said digital
signals onto said main. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to electrical appliance control within a building
and has particular application to appliance control within a domestic
building.
Conventionally, electrical appliance control within a building is achieved
simply by the use of the existing power main together with switches at
fixed locations and switches on the appliances. Remote control is not
conventionally available other than by use of the switches at the fixed
locations and, in recent times, by an ultrasonic link directly to a
specific appliance, such as a television receiver. The problem exists,
therefore, of providing for a more flexible remote control of electrical
appliances in a building. According to the invention, a solution to this
problem resides in the use of control signals supplied to the appliances
via the power main.
Control systems have been disclosed in the prior art (so-called ripple
control systems) in which devices such as recording meters, security
systems and street lamps can be controlled from remote transmitters
permanently connected to the power supply system supplying such devices.
It appears that such systems have been used only for public utilities,
such as electricity boards, and are not suitable for domestic use.
SUMMARY OF THE INVENTION
According to one aspect of the invention there is provided an electrical
appliance control system, characterised by a transmitter unit having input
means for entering the address of a slave unit and means for generating a
digital address signal representing the defined slave unit address and
modulated on a carrier having a frequency a plurality of times greater
than the frequency of the power main, the transmitter unit being coupled
to the main within the building to inject said digital address signal onto
the main, the or each slave unit being coupled to the main within the
building and comprising means for defining an address for that slave unit
and means responsive to said digital address signal, when present on the
main, to render the slave unit operable to effect an appliance power
supply control operation when the responsive means detects that the
digital address signal corresponds to the defined address of said slave
unit, at least one of the transmitter and slave units being releasably
couplable to power outlets of the main so that at least that unit may be
used optionally at various places within the building.
In preferred embodiments the transmitter unit also has means for defining
an appliance operation, e.g. `ON` or `OFF`, and producing a digital
operation signal representing the defined operation and modulated on a
carrier having a frequency a plurality of times greater than the frequency
of the power main, the transmitter unit being coupled to the main to
inject said digital operation signal onto the main, a slave unit when
rendered operable by the digital address signal being responsive to the
digital operation signal to cause the controlling means to function in
dependence upon the content of the digital operation signal.
There is also preferably incorporated into the digital signals a house or
system code which can be unique to that system. The slave unit must then
decode a given system code before it responds to the device or operation
data in the signals. In this way interference between neighbouring
systems, for example different systems used in the same building or in the
same street if electrically coupled, can be reduced.
In order to improve the noise immunity of the system, the digital signal
preferably comprises data in its logical true and logical inverse forms.
The slave unit then preferably has a comparator to compare the true and
inverse data forms and only responds when correspondence is detected by
the comparator.
According to a preferred embodiment pulse duration coding is employed, the
digital signal comprising a plurality of pulses, each pulse comprising a
number of carrier cycles, the number of cycles in a pulse defining the
logic value of that pulse, the slave unit having means for counting the
carrier cycles in each pulse and interpreting the logic value of it on the
basis of whether the number of carrier cycles falls within the first or
second of two different nonoverlapping ranges of numbers, such ranges
being for example between zero and 47, and between 48 and 72. This method
of data transmission is found to minimise the effects of interference on
the transmission of data along a power main.
It is also found advantageous for the pulses to be transmitted close to the
zero crossing of the mains so as to limit interference from transients in
the mains wiring, for example originating from thyristor type controls
close by; which occur predominantly at high mains voltages. So the pulses
preferably occur in the region of zero crossings of the power main signal
and preferably within periods containing a zero crossing and each of a
duration no greater than one eighth (preferably one tenth) of a half cycle
of the power main.
According to another preferred embodiment of the invention, a slave unit is
provided with means for operating a switched appliance manually, without
using the transmitter unit. The slave unit is for this purpose preferably
provided with sense means for sensing a condition of the appliance
indicative that a power switch of the appliance has been operated.
According to a second aspect of the invention, there is provided a
transmitter unit for use in the system of the first aspect, the unit
comprising means for receiving a signal defining a slave unit address and
an appliance operation, means coupled to the receiving means for
generating digital signals comprising pulses of carrier frequency in
digital code defining said address and said operation, and electrical plug
pins for plugging the signal output of the unit into a domestic main
socket to inject said digital signals onto the main.
According to a third aspect of the invention, there is provided a slave
unit for controlling an appliance in a system according to the first
aspect, when having a transmitter unit according to the second aspect, the
slave unit comprising electrical plug pins for plugging the slave unit
into a domestic mains socket, means for connecting an appliance to the
unit, a current control device coupled between the pins and the connecting
means to control the operation of the appliance, means defining an address
for the slave unit, and means responsive to said digital signals coupled
to said pins, the responsive means including a comparator for comparing
the address conveyed by the digital address signal with the address
defined by the defining means and for producing a signal for controlling
the current control device in dependence upon the defined appliance
operation when correspondence of addresses is found.
According to a fourth aspect of the invention, there is provided a slave
unit for controlling an appliance in a system according to the first
aspect, when having a transmitter unit according to the second aspect, the
slave unit comprising means for coupling the slave unit to a domestic
main, means for connecting a lighting appliance to the unit, a lighting
appliance dimming control device coupled between the coupling means and
the connecting means to control the brightness of the appliance, means
defining an address for the slave unit, and means responsive to said
digital signals coupled to said coupling means, the responsive means
including a comparator for comparing the address conveyed by the digital
address signal with the address defined by the defining means and for
producing a signal for controlling the control device in dependence upon
the defined appliance operation when correspondence of addresses is found.
The transmitter unit and slave units are preferably provided with
transformers coupled between the signal paths of the units and the main
for substantially isolating components of the units from the main whilst
allowing the digital signals to be passed between the units and the main
via those transformers.
For a better understanding of the invention and to show how the same may be
carried into effect, reference will now be made, by way of example, to the
accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic diagram of transmitter units and slave units
according to the invention together with a power main and appliances,
FIG. 2 is a circuit diagram of the table top transmitter unit of FIG. 1,
FIG. 3 is a circuit diagram of the hand-held transmitter unit of FIG. 1,
FIGS. 4-9 are block circuit diagrams of parts of the integrated circuit of
FIGS. 2 and 3,
FIGS. 10-12 are timing diagrams of signals received and generated by the
integrated circuit of FIGS. 2 and 3,
FIG. 13 is a circuit diagram of a slave unit of FIG. 1 for switching an
appliance,
FIG. 14 is a circuit diagram of a slave unit of FIG. 1 for controlling a
lighting appliance,
FIG. 15 is a circuit diagram of a slave unit of FIG. 1, in the form of a
plateswitch lighting control unit,
FIGS. 16-19 are block circuit diagrams of parts of the integrated circuit
of FIGS. 13 to 15,
FIGS. 20 and 21 are timing diagrams of signals received and generated by
the integrated circuit of FIGS. 13 to 15.
DETAILED DESCRIPTION OF DRAWINGS
FIG. 1 is a diagrammatic representation of several units of a domestic
appliance control system according to the invention.
In FIG. 1, the power main (9) of a building has power sockets 10a, 10b,
10c, into which can be releasably plugged a table top transmitter 1 and
slave units 3 (an appliance unit) and 4 (a dimmer unit). Electrical
appliances, such as the television set 19 and the lamp 20, are releasably
plugged into these slave units. In addition to the slave units 3 and 4, a
plateswitch dimmer slave unit 5 is incorporated into the system to control
lights which are permanently wired onto the main, such as overhead light
6. The table top transmitter has a keyboard 11 by which data concerning
the operation of the appliances 6, 19 and 20 can be entered. Such data
passes through the mains to the slave units to operate the appropriate
appliance. To distinguish between appliances, each slave unit is given an
appliance code which is set manually by means of a rotary switch (8) at
each slave unit. Another rotary switch (7) is provided both at the slave
units and at the table top transmitter in order that a "housecode" can be
set, this "housecode" being intended to be unique to the house or building
concerned to prevent interference between separate systems which are
electrically coupled--for example houses in the same street.
When it is desired to control one of the appliances, the keyboard is
operated to key in the appliance code concerned followed by the operation
desired, e.g. "on". The transmitter will in consequence develop two
digital signals, the first of which represents the appliance code and the
second of which represents the desired operation. The house code is added
to both digital signals which are passed on to the main in sequence. The
first digital signal is conveyed by the main to each slave unit but only
one of the slave units will respond to this signal, i.e. the slave unit
which contains the house code and appliance code concerned. This
particular slave unit will be enabled by the first digital signal, so that
when the second digital signal arrives it will execute the demanded
operation. Subsequently, that slave unit remains enabled for further
operational orders unit such time that another appliance code is called
for by the transmitter.
In addition to calling one appliance, an "all" key and a "clear" key are
provided to switch on and off the appliances connected to all slave units.
FIG. 1 also shows an auxiliary keyboard unit (the handset 2) which uses
ultrasonic transmission to convey data to the table top transmitter unit
for subsequent encoding and passage onto the main. Handset 2 transmits the
appliance and operation codes to the transmitter unit 1 by way of an
ultrasonic signal (using a carrier frequency of, for example, 40 Khz) and
an ultrasonic receiver in the transmitter unit 1. The transmitter unit 1
will, as before, add the house code to the signal and will in addition
regenerate the pulses with a carrier frequency of, for example, 120 Khz.
FIG. 2 is a circuit diagram of the components of the table top transmitter
of FIG. 1.
In FIG. 2 the keyboard 11 comprises a matrix 11a of switches having three
columns of switches associated with the number keys 1 to 16 and the
operation keys DIM, ON, OFF, CLEAR, BRIGHTEN and ALL. An integrated
circuit 12, preferably an insulated gate field effect transistor
integrated circuit, has facilities for supplying strobe signals S.sub.1 to
S.sub.4 to columns of the matrix of switches of the keyboard. In this
embodiment only three columns are provided so that only signals S.sub.1 to
S.sub.3 are connected to the matrix. Data represented by a key depression
closing a switch of the matrix is thus transferred as a voltage level from
one of the strobe signals to the integrated circuit 12, where it is
converted to a serial five bit code which appears at a serial data output
"SER.OUT". The output "SER.OUT" is coupled by an amplifier, including a
transistor T.sub.4, and a transformer L1 to plug pins 13 by which the unit
can be releasably connected to any power outlet socket of the power main.
By these means the data is injected as a digital signal onto the main.
D.C. power supply to terminals V.sub.SS and V.sub.DD of the integrated
circuit is taken from the pins 13 by means of capacitors C1 and C2,
resistor R1 and diodes D.sub.1, D.sub.2 and D.sub.3.
A house or system code is defined at the unit by rotary switch 7 of a
conventional construction as indicated by FIG. 2. The four bits defined by
the switch 7 are taken to input terminals H1 and H4 of the integrated
circuit. The four bits of the housecode are added to the data entered via
the keyboard and also appear at output "SER.OUT" for injection onto the
mains.
It has been found that interference can be reduced by injecting the data
bits onto the main near the zero crossing points of the mains voltage. To
achieve this, a mains trigger signal is utilised by the integrated circuit
and is obtained as a clipped sine wave of 16 V amplitude by way of
resistors R10 and R17 and diodes D5 and D6. Resistor R17 ensures that the
mains voltage is at zero, the mains trigger is at -5 V, being the
threshold of the input "TRIG" of the integrated circuit. This unit
therefore operates synchronously with the main.
An additional feature of the transmitter unit is an LED diode D7 which
becomes energised when the integrated circuit detects valid input data for
transmission.
Resistor R13, variable resistor VR1 and capacitors CR and CL are coupled to
terminals .phi.R and .phi.L of the circuit adjustably to set the frequency
of its internal clock which inter alia sets the frequency of the carrier
of the digital output signals.
When the hand held transmitter (2) is used in conjunction with the system
an ultrasonic serial data signal, representing a key depression,
transmitted therefrom is received by an ultrasonic transducer 14,
amplified by threestage amplifying circuitry, including transistors T1 to
T3, and entered into the integrated circuit 12 at the serial data input
"SER.IN". This data is subsequently passed to output "SER.OUT" and thus
onto the main after the housecode has been added to the data.
The hand held transmitter, the circuitry of which is represented
schematically in FIG. 3, comprises an integrated circuit 12 of identical
form to that employed in FIG. 2. However terminal U/S is not connected to
neutral so that it becomes suitable for running off a low voltage d.c.
supply provided by a 9 volt battery 15 in that most of the circuit in this
condition is deenergised until a key is depressed. A serial bit code for
each key depression is set up by the integrated circuit and passed to the
output transducer 16.
FIGS. 4 to 9 are block circuit diagrams of the components of the integrated
circuit of FIG. 2 and FIGS. 10 to 12 are timing diagrams showing the
timing relationships of the control signals and output data signals
associated with the integrated circuit of FIG. 2.
A general description of the function of the integrated circuit will now be
given, followed by a detailed description of each part.
Data entered by the keyboard of the transmitter is encoded and stored as a
five bit data signal in the keyboard input logic 25, 26 of FIG. 6, from
which it is transferred to stages f to k of input register 27. On receipt
of a signal TP2 generated just after the zero crossing of the mains
voltage, the five bit data signal, together with a four bit housecode from
the rotary switch (encoder) 7, is transferred to a transmission register
22 and subsequently emitted via output gating circuitry 40 (FIG. 7) to the
output "SER.OUT."The output signal is synchronised to the zero crossings
of the mains voltage, is normally repeated at least once, and has a start
code and an end code inserted at appropriate parts. These and other
features of the output signal are governed by system control bistables B2
(FIG. 6), B3 and B4 (FIG. 8), a transmission timer (FIG. 8) consisting of
a six stage counter 28, and a transmission delay timer 31 (FIG. 7)
comprising an eight stage counter. The form of part of a typical message
is shown as "SERIAL OUT" in FIG. 2. This example is suitable for a single
phase or three phase power main and for this purpose each bit of the
message is generated three times in synchronism with one phase, the first
occurrence being just after a mains voltage zero crossing and the others
after preset time intervals so as to occur approximately at 60.degree.and
120.degree., i.e. in the region of the zero crossings of the other two
phases if present. These repetitions of the bits are controlled by the
transmission delay timer 31 (FIG. 7), and the sequencing of successive
bits are controlled by the states of the transmission timer (FIG. 8) these
states being identified below the waveform of "SERIAL OUT" in FIG. 12. The
transmission timer is clocked through its states in synchronism with the
zero crossings of one of the phases.
During the first four states of the transmission timer (1 to 4) a start
code (1110) is generated. During the next eight states (5 to 12) data
representing the housecode in alternate logical true and logical inverse
form is sent, and during the next ten states (13 to 22) data representing
the operation or address code, similarly in true and inverse form, is sent
(FIG. 12 specifically shows as an example one of the operation codes). The
message is then repeated at least once under circumstances to be described
hereinafter with reference to FIG. 8.
FIGS. 4 to 9 will now be described in more detail.
FIG. 4 is a block circuit diagram of clock circuitry including an
oscillator 37 designed so that its output frequency is substantially
independent of supply voltage. This oscillator produces a stable a.c.
waveform adjustable over a frequency range including 120 KHz. The exact
value is adjustable by means of resistor VR1 as required. This waveform
feeds a clock generator 38 comprising three divide-by-two circuits for
producing clock pulses .phi.1 and .phi.3 and a timing pulse TB. Additional
clock pulses .phi.2 and .phi.4 are produced from .phi.1 and .phi.3 by a
circuit 41 responsive to the leading and trailing edges of .phi.1 and
.phi.3. Clock pulses .phi.1 to .phi.4 are used for four-phase control of
the transistors of the integrated circuit and are also used for control
purposes where indicated in the subsequent figures. Pulse TB clocks a
strobe counter 36 from which the strobe signals S1 to S4 are generated.
These are the signals which strobe the keyboard 11 as described with
reference to FIG. 2.
Signals SAMPLE KEYBOARD, START SCAN and END SCAN are produced when
appropriate inputs are present at gates 39a, b, c, as shown in FIG. 4.
The time relationships of the timing pulses .phi.1, .phi.3, TB and S1 to S4
and the principal signals involved in the recognition and entering of
keyboard data will now be described in more detail with reference to FIG.
10.
With the transmitter unit adjusted to operate at a carrier frequency of 120
KHz, the time period between the .phi.1 pulses is 33.3 .mu.s and each
pulse .phi.1 is 8.33 .mu.s wide. Identical dimensions apply to the pulses
.phi.2, .phi.3 and .phi.4 but these are 90.degree., 180.degree.and
270.degree.out of phase with the .phi.1 pulses. Pulses .phi.1 and .phi.3
are shown in the first two lines of FIG. 10, but pulses .phi.2 and .phi.4
are omitted for clarity. The next line shows TB pulses, which are produced
when .phi.1 pulses are fed to a .div.2 counter (FIG. 4) and therefore
have a frequency half that of the .phi.1 pulses. The TB pulses are fed as
a clock pulse to the strobe counter 36 (FIG. 4) so that the strobe pulses
S1 to S4 have timing relationships as shown in FIG. 10. The period of each
of the strobe pulses is 267 .mu.s and each has a duration of 66.7 .mu.s.
The eighth line of FIG. 10 shows the "START OF SCAN" signal which is
produced following the start of each pulse S1 and in synchronism with the
.phi.3 pulses.
The "END OF SCAN" signal is produced towards the end of S4 in synchronism
with the .phi.3 and TB pulses.
FIG. 5 shows the logic circuitry employed to energise the integrated
circuit and to generate a resetting signal POC. A power input 44 to the
integrated circuit is connected to the majority of elements of the
integrated circuit via a gate 42 and lead 43 so as only to energise these
elements when an OR gate 45 receives an input signal. On the other hand
the gates 42 and 45 are permanently connected to input 44 as are
appropriate elements of the keyboard input logic and the strobe counter so
as to allow a signal AK to be developed even though power has not been
supplied to lead 43. The integrated circuit 12 for the table top
transmitter of FIG. 2 has input U/S connected to VSS thereby keeping it
"high" to enable the gate 42 to keep the circuit fully energised all the
time. As shown in FIG. 3, however, for the hand held transmitter unit, U/S
is not connected, and so power is only sent to the majority of elements of
the integrated circuit when AK is "high", that is when a key is depressed.
This conserves power in the hand held transmitter unit making it possible
to power it usefully by a 9 V battery 15 as shown in FIG. 3. In that case
full power is maintained by a bistable 46 until the end of a transmission
from the hand held unit.
FIG. 6 shows keyboard input logic and the input register.
Key input terminals K1 to K8 of the integrated circuit are connected to the
inputs of a binary encoder 25, the three bit output of which is connected
to three stages of a store 26 which also receives information from strobe
inputs S2 to S4 via "OR" gates 47. Store 26 is connected via "AND" gates
48 to stages f to k of input register 27. Terminals K1 to K8 are also
connected via gating to bistable B1 which produces "any key" signals Ak
and AK. Inputs to a gate 49 as shown in FIG. 6 control the generation of
pulse TP1 which enables gates 48. An "AND" gate 50 is also so connected to
the output of store 26 as to emit a signal whenever it detects a
brightening on dimming operation code in the store 26.
A bistable B2 is arranged to be set by the pulse TP1 to produce a signal
"TRANSMIT" shown in FIG. 10. Bistable B2 can also be set by a signal from
an "AND" gate 57 responsive inter alia to the output of a comparator 35
which is connected to compare the contents of stages f to k with the
contents of stages a to e of the input register 27. A bistable 58 is
additionally provided to detect input register overflow and its output OVF
is connected to one input of the "AND" gate 57.
FIG. 7 shows "AND" gates 21 with inputs from stages f to k of the input
register 27 of FIG. 6 and from H1 to H4 (the housecode data input
terminals). A lead for conveying control signal "TP2" is connected to
enable all the gates 21. The outputs of the gates 21 are connected to
respective stages 1 to 9 of transmission register 22 which is clocked by
the output signal C.phi.3 of gate 29 activated by signals as shown in FIG.
7, the form of signal C.phi.3 being indicated in FIGS. 11 and 12.
The output of the register 22 is from its first stage (1) and into the
output gating circuitry 40, described in more detail later.
FIG. 7 also shows a Null Detection circuit 59 comprising a two stage
counter, connected to the "TRIGGER" input of the integrated circuit,
clocked by pulse .phi.3, and connected to gating elements such that the
pulse Trig .phi.3 is produced at each zero crossing of the mains voltage
as indicated in FIG. 11. The pulse Trig .phi.3 is connected to the reset
inputs of transmission delay timer 31 so that the timer 31 is reset at
each mains zero crossing. Transmission delay timer 31 comprises an eight
stage counter with a clock pulse input of signal .phi.1, and a decoder
producing the signal "ENABLE" (which is illustrated in FIG. 11) and the
signal "ENABLE.sup.1 ". The output signal "ENABLE" of the decoder is
connected to the input of gate 30 of the output gating circuitry 40. The
decoder also has 50 Hz or 60 Hz selecting inputs for selecting respective
portions of the decoder to give either the delays shown in FIG. 11 or
corresponding delays for 50 Hz.
FIG. 8 shows system control bistables B3 (LOCKOUT) and B4 (BUSY) connected
together via "AND" gate 51 which, when provided with inputs as shown,
produces an output signal TP2, the form of which is shown in FIG. 10,
through a transistor, connected to the VDD input of the integrated
circuit, to a light emitting diode D7 which indicates that the transmitter
is transmitting. FIG. 8 also shows a transmission timer which comprises a
six stage counter 28, decoding gates 61 to 64 for decoding states of the
counter 28, and bistables B5 (.gtoreq.2) and B6 (END) both having reset
inputs connected to receive the signal "TP2", B5 being connected to B6 via
gating as shown and described in more detail later. FIG. 8 also shows six
stage timeout counter 33 which is clocked by the strobe signal S1 and
reset each time a key is depressed by the signal AK via "OR" gate 60.
Outputs of counter 33 are connected to gate 65 so that the signal "SAMPLE"
is generated. Outputs of counter 33 are also connected to gates 66 and 67,
the outputs of which are connected to further gates as shown in FIG. 8 to
produce signal "S.R. RESET" 20 msec. after the "START OF SCAN" signal is
produced, so that bistable B2 (FIG. 6) is not reset by signal "S.R. RESET"
until B1 (FIG. 6) has remained reset for 20 msec.
FIG. 9 shows eight stage input code counter 32 clocked by the input signal
present at the input "SER. IN" of the integrated circuit. Decoding gates
68, 69 and 70 have outputs connected to set bistables B20, B21 and B22 for
generating signals "1 BLOCK", "END CODE" and "VALID BLOCK" respectively as
shown in FIG. 9. A signal "BLOCK END" is produced in .phi.1 time when
signal "SAMPLE" is generated (from the circuitry of FIG. 8) and bistable
B23 is reset, or when signal POC is generated (from the circuitry of FIG.
5). Signal "BLOCK END" resets counter 32 and bistables B20, B21 and B22.
Input "SER. IN" of the integrated circuit is also connected to three-stage
counter 34 the outputs of which counter are connected via "AND" gate 71 to
the "set" input of bistable B23. Signals .phi. and .phi.' are generated at
outputs of "AND" gates 72 and 73 respectively when appropriate inputs as
shown in FIG. 9 are present.
It will be noted that the circuitry described above and illustrated in FIG.
9 is only operative in the integrated circuit of the table top transmitter
unit (1 in FIG. 1) and then is only used when the hand-held transmitter
unit (2 in FIG. 1) is used to send data by an ultra-sonic signal to
transducer 14 (FIG. 2) in the table top transmitter unit (1 in FIG. 1).
A general description of the response of the circuit elements described
above with reference to FIGS. 4 to 9, to the signals illustrated in FIGS.
10 to 12 will now be given.
Firstly, when power is applied to the transmitter unit 1 (i.e. it is turned
"ON"), power is applied to the integrated circuit 12 of FIG. 2 and hence
enables "OR" gate 45 (FIG. 5) to enable gate 42 to pass the power along
line 43 to the rest of the circuitry of the integrated circuit. The
circuitry shown in FIG. 4 thus becomes operative to generate the timing
pulses indicated. Each "START OF SCAN" pulse (shown in line 8 of FIG. 10)
resets the bistable B1 (FIG. 6), to cause the five-bit store 26 to open in
readiness to receive data. | | |
