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CROSS REFERENCE TO RELATED APPLICATIONS
Alan J. Lawrence, et. al. Ser. No. 888,607 filed Mar. 17, 1978, Expandable
Digital Switching Network.
Alan J. Lawrence, et al., Ser. No. 888,582, filed Mar. 17, 1978, Multiport
Digital Switching Element.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to distributed control digital
communication and computer systems, to digital switching networks and to
telephone exchanges for providing expandable subscriber line/trunk traffic
capacity for toll, tandem, rural, local, concentration and expansion
applications. The present invention also relates to multiprocessor or
multicomputer communications systems in which certain of the data
processing functions or other terminal processing functions are provided
by one group of processors or computers while other processing functions
associated with different and larger groups of the terminals are provided
independently by a second pooled group of processors, while communication
and data exchange between the two groups of processors or computers is
provided over common transmission paths thru a digital switching network.
The present invention also relates to multi-port switching elements
characterized in that the ports thereof function either as inlets or
outlets depending only upon the network application requirements for
provided one-sided, two-sided or multisided switches in the network.
2. Description of the Prior Art
In modern telephone switching systems, it is presently required that data
representative of the status of the subscriber lines and trunks served by
such a switching system, together with required actions by the switch in
response to various lines and trunks status conditions be stored.
Representative data is path set-up through the network, subscriber class
of service, trunk class of call, directory number to equipment number
translations, equipment number to directory number translations, etc. In
prior art centralized control systems, this data is available in a common
memory, which is duplicated for security and reliability purposes and is
accessible by common control computers for serial operations upon the
extracted data. Multiprocessing common control systems of the prior art
require more than one processor to access the common memory to obtain data
at the same time, resulting in interference problems and an effective loss
of throughput, which increases as the number of processors increases.
Decentralization of control and distributed data processing has evolved in
light of the problems inherent in a centrally controlled system. A prior
art switching system wherein stored program controllers are distributed
throughout the system is described by U.S. Pat. No. 3,974,343. Another
prior art progressively controlled distributed control switching system is
described by U.S. Pat. No. 3,860,761.
Prior art systems have concentrated upon obtaining a high efficiency for
the processing function, with multiprocessing providing increased
processing capability; however, with resultant undesirable interaction
between software packages wherein the modification or addition of features
could interfere with the current working of other features in an
unpredictable manner. A major reason for the problems of prior art common
control architectures, whether or not multiple processors are used, is
that stored program control processing functions are shared in time
between a plurality of tasks which randomly occur on demand of the
originating and terminating traffic, which does not provide for an
efficient operation of the stored software packages.
In accordance with the present invention, there is no separately
identifiable control or centralized computer complex, since the control
for the switching network is distributed in the form of multiple
processors throughout the subsystems, with such distributed processors
providing groups of necessary processing functions for the subsystems
serviced. Thus, groups of control functions for certain subsystems are
performed by processors dedicated to those subsystems; however, other
processing functions of the same subsystems which may be more efficiently
performed by other processors are performed by such other processors.
Also, in accordance with the present invention, a switching network
architecture is provided wherein not only are multichannel digitized PCM
speech samples or data between one terminal and another carried by the
network, but the same channels also contain the path selection and other
control signals for the distributed control, which are carried on the same
transmission paths thru the network. Every terminal, whether carrying data
from a line or trunk or other data source is serviced by a terminal unit
which contains all of the facilities and control logic to communicate with
other terminals via other terminal units and to establish, maintain and
terminate paths thru the switching network to other terminal units. All
interprocessor communication is routed thru the switching network. A group
switch containing switching elements providing both time and space
switching is provided which is modularly expandable without disruption of
service or rearrangement of existing interconnections to provide a growth
from approximately 120 to 128,000 or more terminals, to accomodate
increasing traffic load while performing as an effectively non-blocking
network. A failed switch element is easily and automatically identified,
isolated and bypassed by traffic.
In accordance with the present invention a group switch is provided in
which multiport single sided switching elements are arrangeable in any
inlet/output configuration for example, as 8.times.8 switches containing
space and time switching in a ST configuration. The path selection
throughout the network of switching elements is performed by control
commands carried by the speech channels. Further, reflection switching
facilities provided so that a path set up, for example, in a stage two
switch, when no stage three is yet provided, will be reflected back via
the speech path to form a folded network, while the outlets of the stage
two switch remain available for future connection for network expansion.
The expansion to a third stage would then require connection of the
available outlets of stage two to the inlets of the future stage three
switch.
SUMMARY OF THE INVENTION
A distributed control digital switching system is described in which a
plurality of subscriber lines and trunks are provided with a switched
access to various processing functions shared over a plurality of time
shared multiplexed lines. Each processor of a first group of processors is
dedicated to a group of terminals such as subscriber lines or trunks, and
communicate with processors in a second group to provide pooled processing
functions to one or more of said groups of terminals through a digital
switching matrix. Processors in the first group perform a first set up
processing functions, such as path set up and processors of the second
group perform a second set of processing functions, such as call control.
A multistage switching network provides a modularly expandable digital
group switch, the operation of which is controlled externally from the
terminals to which it is connected, and provides rate synchronous, phase
(bit) asynchronous interconnection among the terminals which are
interfaced and switched. Each processor of the first group is time shared
over a security block of lines or trunks providing hardware interface
therebetween while each processor of the second group provides pooled
functions for a plurality of security blocks of lines and trunks. All
data, speech and control signals are coupled over common transmission
paths.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a distributed control system in accordance
with the invention.
FIG. 2 illustrates the modular expandability of the switching network of
the invention.
FIG. 3 is a simplified block diagram of a multiport switching element of
the invention.
FIG. 4 illustrates one plane of a switching network of the invention.
FIGS. 5(a), 5(b), 5(c) and 5(d) illustrates the expansion of the switching
network of the invention.
FIG. 6 is a block diagram of a line terminal subunit.
FIG. 7 is a block diagram of a trunk terminal subunit.
FIG. 8 is a simplified illustration of the TDM bus of the multiport
switching element of the invention.
FIG. 9 is a block diagram of the logic of one port of the multiport
switching element of the invention.
FIGS. 10(a), 10(b), 10(c), 10(d) and 10(e) illustrate channel word formats
used in the invention.
FIGS. 11(a), 11(b), 11(c) and 11(d) illustrate additional channel word
formats used in the invention.
FIG. 12 illustrates a typical connection between terminals thru the
switching network of the invention.
FIGS. 13(a), 13(b), 13(c), 13(d), 13(e), 13(f), 13(g) and 13(h) are timing
diagrams illustrative of the operation of the switching elements of the
invention.
FIGS. 14(a), 14(b), 14(c), 14(d) and 14(e) are more detailed timing
diagrams illustrative of the operation of the switching elements of the
invention.
FIG. 15 illustrates the TDM bus lines of a switching element of the
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a system block diagram of a distributed control
digital switching system comprising a group switch 10 thru which a
plurality of connections between terminal units are switched to provide
transmission paths for coupling data between terminals serviced by the
terminal units.
As used herein a terminal unit is a subsystem for servicing a group of
terminals which terminate on one first stage switch in every plane of the
group switch. Each terminal unit includes eight access switches through
which data from the terminals is coupled to and from the group switch 10.
As used herein, a terminal subunit is a subsystem of a terminal unit for
servicing a group of terminals which terminate on one security pair of
access switches. Each terminal unit contains four security pairs of access
switches. The PCM data at each terminal is derived, for example, from
telephone line circuits of the type described in detail in the copending
application, Ser. No. 903,458, now U.S. Pat. No. 4,161,633, continuation
of Ser. No. 773,713, now abandoned, filed Mar. 3, 1977, assigned to the
same assignee as is the present invention.
Terminal units 12, 14 and 16 are representatively shown; however up to 128
terminal units or more may be switched by the group switch 10; hence
terminal units 12, 14 and 16 are illustrative only. Each terminal unit has
the capability of interfacing, for example, 1920 subscriber line terminals
or 480 trunks to four terminal subunits, with terminal subunits 18, 20, 22
and 24 illustrated for terminal unit 12.
Thirty-two channel PCM multiplexed digital lines having multiplexed thereon
thirty bidirectional subscriber lines are coupled to the terminal units.
Each terminal unit such as terminal unit 12 is coupled to group switch 10
by a plurality of multiplexed transmission links, each of which
transmission links comprises two unidirectional transmission paths. Each
terminal subunit 18, 20, 22 and 24 of terminal unit 12 is coupled to each
plane of the group switch 10 by two such transmission links, thus for
terminal subunit 18, transmission links 26 and 28 are illustrated as
coupling terminal subunit 18 to plane 0 of group switch 10 and
transmission links 30 and 32 couple terminal subunit 18 to plane 3 of
group switch 10. Similarly, terminal subunit 18 is coupled to planes 1 and
2 of the group switch 10 by similar transmission links. Subunits 20, 22
and 24 are also coupled to every plane of the group switch in like manner
as is terminal subunit 18.
Each transmission link 26, 28, 30 and 32 shown for terminal subunit 18 is
bidirectional in that it includes a pair of unidirectional transmission
paths, each path being dedicated to one direction of data flow. Each
unidirectional transmission path carried thirty-two channels of digital
information time division multiplexed (TDM) thereon in bit-serial format.
Each frame of TDM format is comprised of the thirty-two channels with each
channel having 16-bits of information, and at a bit transmission rate of
4.096 Mb/s. This transmission rate is clocked throughout the system,
hence, the system may be characterized as rate synchronous.
Since, as will be explained hereinafter, the system is also phase
asynchronous, such that there is no required phase relationship as to
which data bits in a frame are received by different switching elements or
by the different ports in a single switching element. This rate
synchronous and phase asynchronous switching system is implemented in the
group switch and in the access switches by a plurality of multi-port
switching elements. When digital speech samples are transmitted anywhere
within the system to or from a particular terminal, the digital speech
samples must be time multiplexed into the correct channels on the
transmission links between switching elements used to connect the
terminals. Time slot interchange is provided by each switching element,
since the channels used to interconnect the terminals may vary.
Time slot interchange, i.e., the transposition of data on one channel to
another channel is well known and described, for example, in U.S. patent
application, Ser. No. 909,583, or continuation of Ser. No. 766,396, now
abandoned, filed Feb. 7, 1977 and assigned to the same assignee as is the
present invention. As will be described, a unique multiport switching
mechanism, which may comprise a 16-port switching element operative as a
thirty-two channel time switch and a sixteen port space switch in
typically less than a single frame time for all inputs thereto is
provided. The digital speech samples may comprise up to 14-bits of the
16-bit channel word with the two remaining bits being used as protocol
bits (to identify the data type in the other 14-bits of the channel word).
Thus the 16-port switching element can be used to switch, for example,
14-bit linear PCM samples, 13-bit linear PCM samples; 8-bit companded PCM
samples; 8-bit data bytes, etc.
Two groups of processors are included within each terminal subunit, such as
terminal subunit 18, the first group of processors, shown as processors
A.sub.0, A.sub.1, . . . A.sub.7, are each dedicated to a separate group of
terminals, called a terminal cluster, and perform a specific group of
processing functions, such as path set-up through the group switch 10 and
the provision of an interface to the terminals within the terminal
cluster. High traffic clusters, such as telephone trunk lines may include
up to thirty terminals whereas low traffic clusters, such as telephone
subscriber lines may contain up to sixty terminals. Each terminal subunit
may interface with up to four high traffic clusters; hence contains four
A-type processors, whereas a low traffic subunit may interface with eight
low traffic clusters and hence contains eight A-type processors. Each
A-processor may include for example, an Intel Corp. Model 8085
microprocessor interface and associated RAM and ROM memory. Thus, each
terminal unit may contain, for example, up to 1920 low traffic terminals
(for subscriber lines) or 480 high traffic trunk terminals. Each terminal
cluster, such as terminal cluster 36 in subunit 18 includes one
A-processor and its associated cluster terminal interface. This cluster
terminal interface is coupled by a pair of bidirectional links 38 and 40
respectively to each of two access switches 42 and 44 within terminal
subunit 18. The access switching elements, such as access switch elements
42 and 44 of subunit 18 are of the same switching element configuration as
are the switching elements of the group switch 10. Access switching
elements 42 and 44 each provide access for subunit 18 to one of a pair of
a second group of processors, such as processors B.sub.0 and B.sub.1 in
terminal subunit 18. Other pairs of B-type processors are included within
terminal subunits 20, 22 and 24, but for purpose of description, only the
B-processors of subunit 18 are illustrated. This second group of
processors, the B-processors, are dedicated to a second group of
processing functions, such as call control (the processing of call related
data, such as signalling analysis, translations, etc.) for the terminals
interfaced by terminal subunit 18 and may also be implemented by Intel
Corp. microprocessor Model No. 8085 or its equivalent. A security pair of
processors is constituted by the inclusion of identical processing
functions in B-processors 46 and 48 and the access switches 42 and 44 for
terminal subunit 18, therefore allowing each terminal cluster such as the
A.sub.0 cluster to select either half of the security pair, i.e., either
B-processor 46 via excess switch 42 or B-processor 48 via access switch 44
in the event of a failure of one half of the security pair, thereby
providing an alternate path.
Referring now to FIG. 2, the group switching matrix 10 having four
independent planes of switching capability, plane 0 at 100, plane 1 at
102, plane 2 at 104 and plane 3 at 106 is illustrated.
A plurality of planes are provided to meet the traffic and service
integrity requirements of the particular system application. In preferred
embodiments, two, three or four planes of switching may be provided, which
will service 120,000 or more terminals, i.e., subscriber lines terminating
in the aforementioned line circuits such as that of application Ser. No.
773,713.
Each plane of switching may contain up to three stages of switching
elements in a preferred architecture. Access switching which selects a
particular plane for a connection may be located within the individual
terminal unit 12, rather than in the group switch 10. The particular plane
of switching elements is selected for a connection by the access switching
stage in the terminal unit. Thus, access switching element 42 in subunit
18 can select, for | | |
