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Claims  |
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We claim:
1. A method of providing a keyer control system for an electronic musical
instrument including a plurality of tone generators each capable of
producing tones, means for supplying input signals for said tone
generators representative of different tones to be produced by said
system, assignment circuit means coupled to said tone generators for
enabling different tone generators to produce tones in response to said
input signals, each tone generator producing a different tone according to
the input signal applied thereto, and a keyer pedestal means coupled with
each of said tone generators for controlling decay mode characteristics of
the tone produced by the tone generator coupled therewith;
the method comprising the steps of forming a first count in a predetermined
sequence of numbers having a total of different numbers at least equal to
the number of tone generators in the system,
assigning a different count of said predetermined sequence of said first
count to a tone generator in one of the conditions of not producing a tone
and producing a tone in a decay mode in order that each such tone
generator is uniquely identifiable by virtue of the count assigned
thereto,
causing a tone generator not producing a tone to produce a tone in response
to the next new input signal representative of a new note as determined by
the counts assigned to the tone generators not producing tones taken in
the predetermined sequence of numbers, and
whenever all tone generators are in one of the conditions of producing a
tone and producing a tone in a decay mode, causing the tone generator
farthest into its decay mode of operation to produce a tone in response to
the next new input signal representative of a new note as determined by
the counts assigned to the tone generators in the decay mode taken in the
predetermined sequence of numbers.
2. A keyer control system for an electronic musical instrument including a
plurality of tone generators each capable of producing tones, means for
supplying input signals for said tone generators representative of
different tones to be produced by said system, assignment circuit means
coupled to said tone generators for enabling different tone generators to
produce tones in response to said input signals, each tone generator
producing a different tone according to the input signal applied thereto,
and a keyer pedestal means coupled with each of said tone generators for
controlling decay mode characteristics of the tones produced by the tone
generator coupled therewith;
said control system further comprising said assignment circuit means
including a first counter means for counting in a predetermined sequence
of numbers having a total of different numbers at least equal to the
number of tone generators in the system, a second counter means associated
with each of said tone generators, each of said second counter means being
coupled to said first counter means and operative to count through said
predetermined sequence of said numbers, and means for loading a different
count of said predetermined sequence of said first counter means into each
of said second counter means associated with a tone generator in one of
the conditions of not producing a tone and producing a tone in a decay
mode in order that each second counter means associated with such a tone
generator is uniquely identifiable by virtue of the count loaded therein,
said assignment circuit means also including means for causing a tone
generator not producing a tone to produce a tone in response to the next
new input signal representative of a new note as determined by the counts
of said second counter means of the tone generators not producing tones
taken in the predetermined sequence of numbers, and whenever all tone
generators are in one of the conditions of producing a tone and producing
a tone in a decay mode, said assignment circuit means causing the tone
generator farthest into its decay mode of operation to produce a tone in
response to the next new input signal representative of a new note as
determined by the counts of said second counter means of the tone
generators in the decay mode taken in the predetermined sequence of
numbers.
3. The combination according to claim 2 wherein said first counter means is
a digital counter means and each of said second counter means are digital
counter means, said means for loading initially causing the storage of a
different count in a sequentially ascending order in each of said second
digital counter means, and means responsive to said input signal supplying
means for changing the count in said first digital counter means to
maintain a count in said first digital counter means and in one of said
second digital counter means representative of the number of tone
generators not producing tones, said assignment circuit means causing the
count of said first digital counter means to be stored in the second
digital counter means unique to a particular tone generator whenever such
tone generator is released to operate in its decay mode, and thereafter
said assignment circuit means changing the count in said first digital
counter means accordingly.
4. The combination according to claim 3 and further including means
operative at predetermined periodic intervals for re-establishing a
predetermined relationship of the counts stored in said second digital
counter means for insuring operation by said assignment circuit means in
accordance with the sequentially ascending order.
5. The combination according to claim 4 wherein said means for supplying
input signals comprises means for supplying binary encoded digital
multiplex signals representative of said different tones to be produced by
said system.
6. A method of providing a keyer control system for an electronic musical
instrument including a plurality of tone generators each capable of
producing tones, means for supplying input signals for said tone
generators representative of different tones to be produced by said
system, assignment circuit means coupled to said tone generators for
enabling different tone generators to produce tones in response to said
input signals, each tone generator producing a different tone according to
the input signal applied thereto, and a keyer pedestal means coupled with
each of said tone generators for controlling decay mode characteristics of
the tone produced by the tone generator coupled therewith;
the method comprising the steps of:
providing a logic signal associated with each of said tone generators
indicative of whether a respective tone generator is enabled to produce a
tone,
providing a predetermined signal when all of said tone generators are
producing tones in response to one of an input signal and the decay mode
characteristic,
assigning a non-enabled tone generator in response to said logic signal and
the absence of said predetermined signal to produce a tone in accordance
with the input signal,
providing a ramp signal responsive to said predetermined output signal,
providing a unique signal representative of the decay characteristics of
the tone controlled by each of said keyer pedestal means,
comparing said ramp signal and each of said unique signals,
determining by said comparison which of said tone generators in farthest
into its decay mode of operation whenever the number of input signals for
different tones to be produced by said system exceeds the number of tone
generators, and
causing the assignment of the tone generator farthest into its decay mode
of operation to a new input signal representative of a new note.
7. A keyer control system for an electronic musical instrument including a
plurality of tone generators each capable of producing tones, means for
supplying input signals for said tone generators representative of
different tones to be produced by said system, assignment circuit means
coupled to said tone generators for enabling different tone generators to
produce tones in response to said input signals, each tone generator
producing a different tone according to the input signal applied thereto,
and a keyer pedestal means coupled with each of said tone generators for
controlling decay mode characteristics of the tone produced by the tone
generator coupled therewith;
said assignment circuit means including logic circuit means coupled to each
of said tone generators for providing a logic signal associated with each
of said tone generators indicative of whether a respective tone generator
is enabled to produce a tone and for providing a predetermined output
signal when all of said tone generators have been enabled to produce
tones, said assignment circuit means in response to the logic signal of
the logic circuit means and the absence of the predetermined signal
enabling a non-enabled tone generator to produce a tone in accordance with
the input signal, a comparator means associated with each of said tone
generators and having a first input and a second input, said comparator
means being operative to compare the signals present at said first and
said second inputs and provide an ouput signal representative of the
comparison, a ramp generator responsive to said predetermined output
signal of said logic circuit means which is rendered operative only when
all of said tone generators are producing a tone, said ramp generator
being operative to apply a ramp signal to the first inputs of all of said
comparator means, and means operative during the decay mode for applying a
unique signal representative of the decay characteristics of the tone
produced by each of said keyer pedestal means to the second inputs of said
comparator means for determining which of said tone generators is farthest
into its decay mode of operation whenever the number of input signals for
different tones to be produced by said system exceeds the number of tone
generators for causing the assignment of the tone generator farthest into
its decay mode of operation to a new input signal representative of a new
note.
8. The combination according to claim 7 and further including busy circuit
means coupled to said tone generators for providing a predetermined output
signal when all of said tone generators have been assigned to produce
tones by said assignment circuit means, and said busy circuit means
further being coupled with said assignment circuit means for rendering
said assignment circuit means operative whenever said predetermined output
signal is produced by said busy circuit means. |
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Claims |
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Description |
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RELATED PATENT AND APPLICATIONS
U.S. Pat. No. 3,955,460, issued May 11, 1976, directed to a digital
multiplex electronic musical instrument and co-pending applications Ser.
No. 834,245, filed Sept. 19, 1977, and now abandoned. Ser. No. 867,907,
filed Jan. 9, 1978, all assigned to the same assignee as this application,
are related to the subject matter of this application.
BACKGROUND OF THE INVENTION
This invention is broadly related to the field of electronic musical
instruments, particularly electronic organs or other electronic musical
instruments having a keyboard such as electronic pianos, accordions and
the like. The term "organ" as used throughout the specification and claims
is intended in a generic sense to include these other electronic musical
instruments. In addition, reference to the actuation of key switches or
coupler switches and the like is intended to cover the actuation of such
switches by whatever means may be employed, such as directly by action of
the musician's fingers or indirectly through intervening levers,
apertures, switch closings, touch responsive switches, multiplex circuits,
etc.
In the design of typical electronic organs today, a system known as a top
octave frequency synthesizer system (TOS) has been developed which
overcomes the need for using a large number of expensive stable
oscillators in the organ. Instead, a single stable oscillator is used to
provide the tones for the top octave of the organ. Divider circuitry then
is employed to generate all of the other related tones, and tuning of such
an organ becomes a relatively simple matter since only a single oscillator
or a small number of oscillators are used in the organ.
While top octave synthesizer systems theoretically can use a single
oscillator for an entire organ this has not proved to be practical. One
disadvantage of employing a top octave synthesizer is that because of the
close interrelationship of all of the divided-down frequencies it is
possible to obtain phase reinforcement or phase cancellation of harmonics
of different tones, which results in very unnatural quality musical
production by the organ. To overcome these disadvantages, a number of
different top octave synthesizers have been utilized in an organ; so that
different notes for different octaves in the different manuals of the
keyboard are produced by different top octave synthesizers. If such
synthesizers are dedicated to a particular block of keys or a particular
part of the organ, however, it still is necessary to use a relatively
large number of synthesizer circuits in the organ.
In the system disclosed in the co-pending patent application Ser. No.
867,907, a limited number of different top octave synthesizer circuits are
used, each of which is capable of producing any note in the organ. The
assignment of different root notes to these different top octave
synthesizer circuits is effected under control of a latch signal
synchronized with the serial digital data representative of key closures
used in the multiplex system with which the synthesizer circuits are used.
In such a system, where the number of different top octave synthesizer
circuits are less than, equal to or only slightly more than the maximum
number of root notes which normally are played by the organ, the
assignment of a previously unassigned top octave synthesizer circuit
ordinarily can be controlled by a suitable logic circuit which senses
whenever a particular top octave synthesizer circuit is idle, waiting for
a new note to be assigned to it. The determination of whether or not a
synthesizer is idle cannot be ascertained merely by sensing the key
closures associated with the initiation and termination of the note
produced by any given top octave synthesizer. This is because there
generally is a decay of the produced tone which extends the tone in
attenuated fashion (with increasing attenuation) after release of the key,
the closure of which initially produced that tone.
Because this characteristic of permitting a top octave synthesizer to
continue to produce a tone in an increasingly attenuated fashion after
release of the key which initiated that tone, it is possible in some
circumstances, to create a demand for more root tones in the system than
there are empty or wholly unassigned top octave synthesizer systems
available to produce the tones demanded. Of course, one solution is to
provide a number of top octave synthesizers which is greater than the
maximum number of tones which could be produced at any time in the organ
whether the tone production results from the actual playing of a key or
the decaying tonal characteristics after a key is released. This approach,
however, is wasteful of synthesizer circuits and substantially increases
the cost and complexity of the circuitry in the organ, and its ultimate
price to the customer purchasing such an organ.
To minimize the number of top octave synthesizer circuits needed and to
continue to permit the organ to produce the most natural sounding musical
characteristics, it is desirable to reassign a top octave synthesizer
circuit to a new note only if such a top octave synthesizer is (1)
operating on the decay tonal characteristics of a note indicating that its
actual playing has been terminated and (2) if such a top octave
synthesizer circuit is the one in the system which is the farthest into
its decay, that is, the one with the most highly attenuated tone output.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved
electronic musical instrument.
It is another object of this invention to provide an improved tone
generation assignment system for an electronic musical instrument.
It is an additional object of this invention to provide an improved tone
generation assignment circuit for an electronic organ utilizing a minimum
number of top octave synthesizer tone generator circuits.
It is a further object of this invention to provide an electronic organ
using top octave synthesizer circuits with a control system for assigning
notes to be reproduced by the organ to top octave synthesizer tone
generator circuits in an order corresponding to which of the top octave
synthesizer circuits is farthest into its attenuated decay mode of
operation.
It is still another object of this invention to provide an electronic organ
utilizing a limited number of top octave synthesizer tone generator
circuits with an assignment control system which assigns the next new note
to the synthesizer circuit which is the farthest into its decay or
attenuated mode of operation when the number of root notes to be produced
exceeds the number of synthesizer circuits.
In accordance with a preferred embodiment of the invention, a keyer control
system is used in an electronic musical instrument which has a fixed
plurality of tone generators each capable of producing tones in the same
octaves of tones which can be played by the instrument. Input signals
which are representative of different tones to be produced by the system
are coupled to all of the various tone generators, and an assignment
circuit is also coupled to the tone generators to enable different ones of
them in a pre-established sequence to produce tones which are represented
by the input signals, each of the tone generators thereby producing a
different tone according to the input signal applied to it. Each of the
tone generators has a different keyer pedestal circuit connected to it to
control the sustain and decay characteristics of the tones produced by the
tone generator; and whenever the number of input signals for different
tones to be produced by the system exceeds the number of tone generators,
a circuit responds to cause the assignment circuit to assign each of the
new excess tone input signals, representative of new notes, to the tone
generator farthest into its decay mode of operation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are a block diagram of a preferred embodiment of the
invention;
FIG. 1C shows the manner in which the sheets of FIGS. 1A and 1B bit
together;
FIG. 2 is a series of waveforms useful in explaining the operation of the
circuit of FIGS. 1A and 1B; and
FIG. 3 is a block diagram of another preferred embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In the drawings, the same or similar reference numerals are used throughout
the several figures to designate the same or similar components.
Referring now to FIGS. 1A-1C, there is shown a keyer control system for use
in an electronic musical instrument, such as an electronic organ of the
type using serial multiplex data generation as disclosed in the
above-mentioned U.S. Pat. No. 3,955,460, the disclosure of which is
incorporated herein by reference. In the digital multiplex electronic
organ disclosed in that patent, a multiplexer circuit controlled by a
system clock operates to present the serial data, representative of key
closures and the operation of coupler switches, in the form of a serial
data signal train which has a fixed number of time slots in it and which
is continuously repeated cyclically in the operation of the system. Such a
multiplexer 10 and a system clock 11 for providing the timing and clock
pulses to the multiplexer circuit 10 are illustrated in FIG. 1A. The
multiplexer 10 and the system clock 11 are operated in the same manner as
described in the above mentioned patent and are the source of the key
closure and coupler switch information which is utilized in the system of
the embodiment shown in FIGS. 1A and 1B to operate various top octave
synthesizer circuits to produce the tones which are represented by the
binary data in the serial data output from the multiplexer 10 as it is
applied over an output lead 13.
In the system shown in FIGS. 1A and 1B, a limited number of top octave
synthesizer circuits are used to generate the various notes of the organ.
Typically, the organ includes twelve such top octave synthesizers, but it
may include only as few as six depending, upon the desired characteristics
of the organ performance. Each of the different top octave synthesizer
sections of the organ may be assigned to any one of the keyboard
multiplexer serial data time slots which represent a key closure, so that
the selection circuitry not only determines which top octave synthesizer
is selected, but also is operated in synchronism with the serial
multiplexed data appearing on the lead 13 to cause the proper root note to
be produced by the selected top octave synthesizer. At different times,
different notes are assigned to the different top octave synthesizers to
permit the maximum flexibility and efficiency in the operation of the
system, as will be more fully understood from the following description.
At the beginning of each frame or new cycle of serial data produced by the
multiplexer 10 on the lead 13, a strobe or frame pulse is applied over a
lead 14 to operate as a system strobe or system reset pulse through a
gating system strobe circuit 15. This strobe pulse is synchronized with
the clock pulses produced by the clock 11 and applied from the clock 11
over another lead to the system strobe circuit 15. The output of the
system strobe circuit 15 is utilized as a reset pulse to reset a four-bit
note-name counter 16 and a three-bit octave counter 17 to an initial or
zero count. In addition, this strobe pulse is applied to an initialize
logic circuit 20 and to a time-out counter 21 to reset both of these
circuits to an initial operating condition.
The four-bit note-name counter 16 and the three-bit octave counter 17 thus
are initially set up for operation and synchronism with the serial
multiplexed data appearing on the lead 13. The note-name counter 16 is
advanced by the clock pulses produced at the output of the system clock 11
(which also synchronizes the operation of the multiplexer 10), so that the
step-by-step advancement of the note-name counter 16 is in synchronism
with the binary serial data appearing on the lead 13. As described in the
above mentioned patent, this data has the different time slots in it
sequentially assigned on a note-by-note basis for successive octaves; so
that the count in the note-name counter 16 corresponds to this
note-by-note progression. Each time a count of twelve (the number of notes
in an octave) is reached, an output pulse is produced by the note-name
counter 16 to advance the three-bit octave counter 17 to its next count.
This operation continues through all of the counts for the number of
octaves of information represented in each cycle of the serial data
produced on the lead 13 by the multiplexer circuit 10.
As described in the aforementioned patent, the first portion of the serial
data stream produced by the multiplexer circuit constitutes the stop and
coupler information. This portion of data is stripped from or blanked from
the serial data stream used in the TOS assignment circuit of FIGS. 1A and
1B by a data stripper and latch circuit 25. This circuit is reset to an
initial or blanking condition by the initialize logic 20 when the power is
first applied to the system by a pulse (PORS) over a lead 28. In addition,
a frame length and comparison circuit 26 is controlled by the octave count
output of the note-name counter 16 to produce an enable pulse after two
octaves of serial data information have been counted. The enable pulse is
applied over a lead 27 to the data stripper and latch circuit 25 to
terminate the data stripping action and to permit the serial data
appearing on the lead 13 to pass through the circuit 25 over a lead 29 to
the other portions of the circuit for use in the operation of the system.
It should be noted that the frame length and compare circuit 26 is enabled
for operation by the system strobe pulse obtained from the output of the
system strobe circuit 15 each time a strobe pulse is applied to it by the
multiplexer 10. Such strobe pulses occur cyclically, once per frame, in
the serial multiplex data stream produced by the multiplexer 10.
The parallel four-bit output from the note-name counter 16 is applied over
a set of four output leads 30 to the data stripper and latch circuit 25
and to a series of seven-bit latch and comparator circuits 40, a different
one of which is associated with each different top octave synthesizer
circuit used in the system. Similarly, the parallel three-bit output from
the octave counter 17 is applied over three parallel output leads 31 to
the seven-bit latch and comparator circuits 40, so that these circuits are
provided with the necessary note name and octave information required for
decoding root notes in any octave which can be keyed in the system by the
appropriate top octave synthesizer circuits controlled by the latch and
comparator circuit. This latch and comparator circuit is the same as the
latch and comparator circuits 13 and 14 of the co-pending application Ser.
No. 867,907.
Reference now should be made to FIG. 2 which illustrates the basic timing
of the system clock and correlates that timing with the signals from the
output of the multiplexer 10, the note counter 16, the octave counter 17,
and the data stripper and latch circuit 25. Waveform A of FIG. 2
represents the 55 kHz clock signals produced by the system clock 11 and
utilized to operate the remainder of the system. Waveform B represents the
strobe pulse which is obtained on the output lead 14 from the multiplexer
circuit 10, and waveform C comprises the internal system strobe pulse
produced on the output of the system strobe circuit 15.
Waveforms D, E, F and G are representative of the parallel four-bit output
from the note-name counter 16. From an examination of FIG. 2 it can be
seen that this sequence resets and repeats itself every twelve pulses in
the output waveform A of the system clock 11. For example, pulse number 1
comprises the first clock pulse associated with the first "note" of the
first octave in the system and pulse number 13 comprises the first pulse
of the first "note" of the second octave in the system, and so on.
Waveforms H, I and J represent the parallel three-bit output of the octave
counter 17 which is reset by the strobe pulse to its initial count at the
beginning of each frame of the serial multiplex data produced by the
multiplexer 10. Waveform K is representative of a typical frame of serial
data representing the closure of three different coupler switches,
illustrated as the four foot, eight foot and sixteen foot switches and
representing the presence of three notes in the keyboard time slots
representative of C, E and G. Of course, in different frames at different
times, different patterns of the serial data of waveform K will exist in
accordance with the actual notes being played on the organ and the
condition of the coupler switches which are operated at various times.
Finally, waveform L of FIG. 2 illustrates the output of the data set strip
line appearing on lead 27 from the output of the frame length and
comparison circuit which shows the initial portion of this output as being
"high" to cause the data stripper circuit 25 to blank out or fail to pass
serial data during the time the serial data stream has the coupler switch
information on it. This signal goes "low" at the time the keyboard
information of the serial data stream is present, thereby causing the data
stripper circuit 25 to pass the serial keyboard data unchanged for the
remainder of each frame following this condition of operation.
As described above, the octave counter is reset at the strobe time of the
multiplexer circuit 10 and is incremented with each roll-over of twelve
counts of the note-name counter 16. An option for the operation of the
octave counter, however, can be provided by way of a control of the type
similar to the operation of the data stripper 25 by the frame length and
comparator circuit 26 to hold the octave counter in its reset state for a
preestablished number of consecutive octaves. This permits the system
shown in FIGS. 1A and 1B to operate with the serial data from a pedel
multiplexer scan or from a standard keyboard multiplexer scan produced by
the manual keyboard scanner. In all other respects, the system operates
the same irrespective of whether the notes produced by it are produced
from a pedalboard of the organ or a manual keyboard.
As mentioned previously, the serial data produced by the multiplexer 10
includes the keyboard data and the control options data. The control
options are in the first two octaves which are scanned, and this control
options data is not used in tuning the top octave synthesizers; so that it
must not be applied to the tuning logic. For this reason, the data
stripper and latch circuit 25 is used, and the serial data is gated so
that all of the information in the first octave and, as illustrated in
waveform L of FIG. 2, the first two clock periods of the second octave are
removed by the data stripper circuit 25. This option data is not used in
the system of FIGS. 1A and 1B, but it is utilized in the multiplex system
of the aforementioned patent and reference should be made to that patent
for the manner in which the option shift register latch circuits are
operated for storing and utilizing this data.
An additional digital function is required in the system besides the clock
strobe and serial data function and that is the initialization of the
system operation. The initializing circuit 20 is employed for two basic
reasons. One is to reset all of the chip control logic and the second is
to assign a sequence of numbers to several internal bookkeeping counters
45, one of which is associated with each one of the top octave synthesizer
circuits 47 in the system. The bookkeeping counters 45 determine the order
in which the different top octave synthesizer and coupler divider circuits
47 are assigned the tuning information.
Once the power supply of the system is activated and the first system
strobe is obtained from the strobe circuit 15, a reset logic circuit 33
supplies a reset pulse to the initialize logic 20 to commence its
operation. The reset time is under external control from other circuitry
of the organ (not shown). Upon the release of the first reset pulse from
the circuit 33, the initialize logic 20 generates an initialize "shift"
output pulse on a shift output lead 34. This pulse is applied to the
signal input of a one-bit shift register 46 associated with the first top
octave synthesizer circuit 47 in the sequence of synthesizer circuits
illustrated in FIG. 1B. This shift signal then is shifted with each 55 kHz
clock pulse from the system clock 11 to the succeeding one-bit shift
register stages 46 in a conventional manner. In addition, a second output
of each of the one-bit shift registers 46 is connected to the "load" input
of its corresponding bookkeeping counter 45 to cause the bookkeeping
counter 45 to load into its counting stages a count equal to the count
appearing on the parallel output leads from a master counter 50 (FIG. 1A).
The master counter 50 is reset to an initial count by the initializing
logic 20 when the system is first placed into operation. This initial
count is a count zero and it is stored in the first (the leftmost one)
bookkeeping counter 45 when the first shift signal is shifted out of the
first one-bit shift register 46 associated with that bookkeeping counter.
As the clock pulses continue to be applied to the shift registers 46, the
master counter 50 also is advanced one count for each clock pulse by
gating such pulses through the initializing logic 20 to a lead 35 and
through an increment control gating circuit 54 to the counter 50. The next
bookkeeping counter in the sequence then is enabled at the second clock
pulse to store the second count from the master counter 50, and so on
until all of the bookkeeping counters 45 store numbers in ascending order
determined by the outputs from the master counter 50. In this way, the
first bookkeeping counter 45 (the leftmost one) stores a zero, the second
stores a one, the third stores a three, and so on.
At this point in the system operation, all of the bookkeeping counters 45
have a number stored in them that dictates the order in which the related
top octave synthesizer circuits 47 are assigned tuning information. Once
the entire sequence of bookkeeping counters 45 have been filled with the
counts providing this information, the initializing procedure for the
bookkeeping counters is completed. This is all accomplished during the
first two frames of the multiplex signal as counted by the first two
stages of the time-out counter 21. At the end of this time, the enable
signal from the counter 21 to the logic 20 terminates, disabling the gates
of the logic 20.
The reset output from the logic circuit 33 also programs all of the
seven-bit latch and comparator circuits 40 with a number which does not
correspond to a valid note count, so that no two top octave synthesizer
circuits 47 can subsequently be assigned with the same keyboard position.
This could happen by chance, if more than one top octave synthesizer
circuit 47 would initially power up with the same valid keyboard time slot
number. Then if any two units were assigned the same keyboard time slot,
the two units would play and be assigned new notes in unison, thereby
effectively reducing the system capacity, so long as this condition
existed.
The time-out counter 21 also comprises an additional part of the
initializing logic. This counter operates to provide a reinitialization or
a reactivation of the initializing logic 20 for resequencing the
bookkeeping counters 45 anytime no keyboard serial data is entered into
the system for a period of approximately five to ten seconds. This time
period can be varied in accordance with the particular operating
characteristics desired in the system. The actual time of the time-out
counter 21 is dependent on the multiplexer frame length and the system
clock rate of the clock circuit 11. This is necessary because a twelve
stage counter clocked by the system strobe comprises the timing element of
the time-out counter 21.
Control of the bookkeeping counters 45 after the initialization operation
is provided by adaptive sustain logic in keyer pedestal logic circuits 49,
one of which is provided for each of the different top octave synthesizer
circuits 47. The keyer pedestal logic circuits 49 provide the attack,
sustain and decay operation of the top octave synthesizer circuits 47 in
accordance with the key closure and key release data in the serial data
appearing on the lead 29, and as controlled by the output of the seven-bit
latch and comparator circuit 40 associated with each individual keyer
pedestal logic circuit 49.
As is explained more fully subsequentially, the keyer pedestal logic 29
functions to insure that all of the top octave synthesizer circuits 47 in
the system must have been assigned a different keyboard position (a
different root note) before any top octave synthesizer circuit 47 may be
reassigned to a different note. When the system has been completely
assigned, all of the top octave synthesizer circuits 47 are actively
engaged in the production of a root note. However, it is possible (in fact
more likely) that some top octave synthesizer system 47 in the system does
not have a key closure (as determined by the keyer pedestal logic 49)
currently associated with that note assignment. Such a top octave
synthesizer is in its released or decay mode of operation, and if it has
been in this mode longer than any other top octave synthesizer circuit 47
in a similar condition, it will be the next one to be reassigned a new
note in the system.
An additional requirement which is controlled by the keyer pedestal logic
circuits 49 and latch circuits 40 is that of causing a top octave
synthesizer circuit 47 to rekey or be reassigned with a note if the key
closure for that note is associated with the same note being produced or
previously produced by that top octave synthesizer circuit. This occurs to
cause such a top octave synthesizer circuit to rekey for the same note
which it was previously producing even if that synthesizer circuit is out
of the assignment sequence determined by the state of the count in the
bookkeeping counters 45. As stated previously, except for this condition,
the assignment sequence of the top octave synthesizer circuits 47 is
controlled by the count in the bookkeeping counters associated with each
of the different top octave synthesizer circuits 47.
Operation of the assignment logic to cause a particular top octave
synthesizer circuit 47 to produce a note and the sustaining of that note
under control the keyer pedestal logic 49 is described next. First, the
seven-bit latch and comparator circuits 40, as mentioned previously, have
parallel inputs applied to them from the note-name and octave counters 16
and 17 along with an input from a different latch load logic circuit 48
for each circuit 40. The seven-bit latch and comparator circuits 40 are
operated by the output of the latch load logic circuits 48 to store the
seven-bit note-name and octave number that is on the latch inputs whenever
a load signal is generated by the latch load logic circuit 48 associated
with any one of the latch and comparator circuits 40.
Assume initially that none of the top octave synthesizer circuits 47 are
producing a note and that the system is in its start-up or initial state
of operation. In this state, as described previously, the bookkeeping
counters each have stored in them, following the initializing sequence, an
increasing number obtained from the master counter 50 with the leftmost
bookkeeping counter 45 of FIG. 1B storing a zero. An output of the
bookkeeping counter 45 which has a zero stored in it is applied to its
associated latch load logic circuit 48 to enable that latch load logic
circuit for operation. The latch load logic circuits for the other top
octave synthesizer circuits associated with bookkeeping counters 45
storing other numbers are not enabled by those bookkeeping counters. As a
consequence, the first note in the first keyboard time slot which is on
the serial data signal line 29 occurs in time coincidence with the outputs
of the note-name and octave counters 16 and 17 which correspond to that
note. This note is represented by the first pulse in the keyboard closure
portion of the serial data signal train; and when it is applied to the
latch load logic circuits 48, it causes the enabled latch load logic
circuits 48 to produce a "load" signal pulse to the seven-bit latch and
comparator circuit 40 associated with it to lock or latch that note into
the comparator circuit 40. The output of the comparator circuit 40 in
turn, is applied to the top octave synthesizer and coupler divider circuit
47 connected to it to cause the top octave synthesizer circuit 47 to
produce the root note corresponding to this first pulse in the serial data
signal train.
Each time an assignment takes place in the system, all of the bookkeeping
counters 45 are decremented by one count as well as the master counter 50.
This decrement pulse is produced by the keyer pedestal logic 49 which is
triggered into operation by the pulse in the serial data signal coincident
with an output from the latch and comparator circuit 40 storing the note
data. This decrement pulse is applied over a lead 52 from the output of
the keyer pedestal logic 49 to the inputs of a decrement control
coincidence gating circuit 53 and an increment control gating circuit 54.
The circuits 53 and 54 respond to signals of opposite polarity from the
keyer pedestal logic circuits 49; so that when a keyer pedestal logic 48
produces an output representative of a key closure, the decrement control
circuit 53 produces an output pulse on a lead 56 to decrease the count in
the master counter 50 (this count previously was at its maximum following
the initialize circuit function) and to decrease the count in all of the
bookkeeping counters 45 in the system by one count represented by this
single pulse on the lead 56. The counter 45 which already stored a zero
count is unchanged; but all of the other bookkeeping counters are
decremented by one count to cause the next bookkeeping counter to the
right of the first bookkeeping counter 45 to then store the zero count,
while the counter adjacent that counter on the right then is decremented
from a count of two to one, and so on. As a result, the next top octave
synthesizer latch load circuit 48 which is associated with the next
bookkeeping counter 45 having a zero count is then enabled.
The initialization sequence causes the master counter 50 initially to store
a number which is one bit higher than the highest number stored in any of
the bookkeeping counters 45. Thus, when this decrement pulse appears over
the lead 56 and is applied to the master counter 50, its count is
decremented by one; but the count in the counter 50 is still one bit
higher than the highest number in any of the bookkeeping counters 45.
When the keyer pedestal logic circuit 49 for the first top octave
synthesizer circuit 47 assigned a note is operative to control the attack,
sustain and decay of that note, a signal is applied from the output of the
keyer pedestal logic 49 to the bookkeeping counter 45 associated with that
top octave synthesizer circuit to prevent it from applying any further
enabling signals to the latch load circuit 48 associated with that
bookkeeping counter. As a consequence, the next pulse in the serial data
stream applied to all of these latch load circuits 48 causes a load signal
to be supplied by the latch load logic circuit 48 associated with the next
bookkeeping counter set to zero. The seven-bit latch and comparator
circuit 40 for that note generating unit of the system then is latched, as
described previously, and the sequence is repeated for the next top octave
synthesizer circuit 48 which is assigned the next note. This sequence of
operation of decrementing the bookkeeping and master counters and enabling
different ones of the note assignment units in sequence continues for the
remaining pulses in the serial data stream signal on the lead 29.
Since the serial data stream is a cyclically repeating frame of serial data
and since the keying of a note generally extends over many frames of this
serial data, it is necessary to prevent data pulses in subsequent frames
which are representative of key closures already assigned to top octave
synthesizer circuits from being reassigned to different top octave
synthesizer circuits. This is controlled by the comparator portion of the
seven-bit latch and comparator circuit 40. The comparator circuits 40 are
sampled in synchronism with the serial data stream by the clock pulses on
the output of the system clock circuit 11. Any time the output of the
four-bit note-name counter 16 and the three-bit octave counter 17 applied
to the inputs of the comparator portion of the latch and comparator
circuit 40 compare with or agree with the stored note and octave data
previously latched into a comparator circuit 40, an inhibit pulse is
applied from the output of the comparator circuit 40 in parallel to all of
the latch load logic circuits 48 to prevent any of the latch load logic
circuits 48 from passing a load signal to their respective latch and
comparator circuits. As a result, once a note has been keyed and assigned
to a particular top octave synthesizer circuit 47, it continues to be
produced by that top octave synthesizer circuit 47 and the rekeying of
that same note in a different top octave synthesizer circuit 47 is
prevented.
If a keyed relating to an assigned top octave synthesizer circuit 47 is
released, the keyer pedestal logic circuit 48 produces a signal to the
corresponding bookkeeper counter 45 associated with such a top octave
synthesizer circuit to cause the bookkeeping counter 45 to store the count
presently appearing at that time in the master counter 50. At the same
time, an opposite polarity pulse is applied over the lead 52 to the
increment control logic 54 and the decrement control logic 53 to cause the
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