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BACKGROUND AND FIELD OF THE INVENTION
This invention relates to the art of video display of images representing
data characters or symbols or other graphical images.
The invention is particularly applicable for use in conjunction with a
video display system employed in text editing and the like and will be
described in conjunction therewith; although, it is to be appreciated that
the invention has broader applications as it may be used in various video
displays wherein it is desired to modify one video image with another.
Video display systems having the capability of displaying data characters
and for modifying video characteristics of such data characters are known
in the art. Examples of prior art patents on the subject include the U.S.
Pat. to R. C. Williams Nos. 3,895,374, 3,895,375, and 3,896,428. These
patents each teach video modification of the display of a data character
such as inversion in appearance, intensification, and underlining. One or
more of these modifications may be made to a data character. The apparatus
disclosed in those patents by employs a data stream wherein the data
characters are encoded in binary form and are preceded by a binary encoded
attribute character which commands the attribute or modification to be
made to the data characters following the attribute character. The
attribute character is a multi-bit character with each bit being
representative of one of several attribute modifications which may be
made.
A notable problem with such display systems as described above is that
logic circuitry must be employed to decode each multi-bit attribute
character to decide which modification or modifications are to be made to
the visual images representing the data characters following the attribute
character. The video image of each data character is formed by obtaining
video instructions for that character from a look-up table, such as a read
only memory. These instructions are supplied to a video generator which
may include a T.V. raster scan for forming segmental dot patterns or dot
slices of each of a plurality of characters forming a character line.
Several scans are made until each character of the character line has been
formed. Logic circuitry must be employed to respond to the attribute data
character to make the appropriate video modifications to the images of the
data characters being formed. The complexity of such logic circuitry is at
one level with such enhancements as intensification or inversion in
appearance since each dot position is enhanced in the same fashion.
Consequently, only one piece of information is required by the logic
circuitry. The logic circuitry required becomes far more complex for such
attributes or enhancements as strike-through, underlining, or cross hatch
because each of these require that the dot pattern of the enhancement be
combined with the dot pattern representing the visual image of the data
character. Moreover, such complex logic circuitry to provide these
attributes or enhancement would not be programmable in the field.
Consequently, the user of such equipment would be limited to those
attributes or enhancements provided by the terminal manufacturer.
Another disadvantage of such video display terminals as that discussed
above is the inability to easily create graphical images which combine the
visual characteristics of a data character from one library or set of data
characters such as the English alphabet, with the visual characteristics
of other data characters or graphical images from an independent,
nonrelated library or set of graphical images. For example, an editor may
want to change the meaning of the letter "O" taken from the English
alphabet. If a horizontal bar could be placed through the letter "O", then
the meaning of the letter "O" has been changed to theta, a character taken
from the Greek alphabet.
Thus it would be desirable to provide a plurality of storage libraries each
storing video instructions for forming a set of symbols or data characters
or other graphics and the like such that when a particular symbol or
character or graphics is called for, its video image may be combined with
the video image taken from a different library to form a graphical image
having the combined video characteristics of the various symbols,
characters, or graphics taken from the various libraries.
SUMMARY OF THE INVENTION
It is therefore, a primary object of the present invention to display video
image of one type of graphics (such as a data character) in combination
with the video image of a another type of graphics (such as a symbol) so
as to obtain an image having the combined video characteristics thereof.
It is a still further object of the present invention to provide
improvements in modifying the video appearance of the image of a data
character without requiring complex logic circuitry.
It is a still further object of the present invention to provide
improvements in modifying the video appearance of the image of a data
character so as to change its meaning.
It is a still further object of the present invention to provide
improvements in modifying the video appearance of images representing data
characters wherein such modifications include cross hatch, strike-through,
underline, italic and dotted underline and these are obtained from a
storage library means containing the video display instructions for
forming each of these enhancements and that these instructions be combined
with data character image forming instructions obtained from a similar
storage library for forming the image of the data character with one or
more of these enhancements.
It is a still futher object of the present invention that the storage
facilities for the sets of data characters or symbols or other graphics be
field programmable so that a user may devise his own sets of graphics to
obtain his own combinations of graphical images and the like.
In accordance with one aspect of the present invention, the video display
system displays video images of data characters or other graphics with
video modifications being made thereto. A coded data character is provided
which represents a first graphical image from a first library, such as a
font, of related images to be displayed. A second coded data character is
provided which represents a second graphical image from a second library,
such as a font, of related images wherein the first library of related
images is independent of the second library of related images. A storage
facility is provided for each library with the facility storing video
display instructions for forming each character or graphical image in the
library of graphical images. The storage facility for the first library of
images is interrogated by the first coded data character to obtain
therefrom the video display instructions for forming the image represented
by that data character. The storage facility of images for the second
library of graphical images is interrogated by the second coded data
character to obtain from the storage facility the video display
instructions for forming the graphical image represented by that data
character. The video display instructions for forming the video image of
the character from the first library are combined with the instructions
for forming the graphical image from the second library. The combined
video display instructions are employed for forming a graphical image
having the combined video characteristics of the images represented by the
first coded data character and the second coded character.
In accordance with a more limited aspect of the present invention, one of
the storage facilities referred to above is used for storing video display
instructions for forming each data character taken from a font of data
characters and another storage facility is used for storing video display
instructions for each of a plurality of enhancement characters such as
cross hatch, strike-through, underline, italic and dotted underline.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects and advantages of the invention will become
more readily apparent from the following description of the preferred
embodiment of the invention as taken in conjunction with the appended
drawings wherein:
FIG. 1 is an overall system block diagram illustrating for an application
of the present invention;
FIG. 2 is a schematic-block diagram illustration of a video display
terminal in accordance with the present invention;
FIG. 3 is a schematic illustration of the keyboard layout for the keyboard
of the terminal illustrated in FIG. 2;
FIG. 4 is a schematic-block diagram illustration of the CPU and interface
circuitry;
FIG. 5 is a schematic-block diagram illustration of the input/output
control circuitry;
FIG. 6 is a schematic-block diagram illustration of the memory and its
interface with the common bus structure;
FIG. 7 is a schematic illustration of the display screen of the terminal
illustrated in FIG. 2;
FIG. 8 is a schematic illustration of the line vector table in the main
memory;
FIG. 9 is a schematic illustration showing the manner in which bytes of
data are stored in a display buffer in a single column mode;
FIG. 10 is similar to that of FIG. 9 but showing the display buffer in the
dual or split screen mode;
FIG. 11 is a schematic illustration showing the manner in which enhancement
data and character data are arranged for a character line;
FIG. 12 is a schematic illustration showing the format of a data word;
FIG. 13 is a schematic illustration showing the format of an enhancement;
FIG. 14 is a schematic-block diagram illustration of the timing generator
circuitry;
FIG. 15 is a schematic-block diagram illustration of the video generator
circuitry;
FIGS. 16a through 16i are waveforms useful in understanding portions of the
circuitry described herein;
FIG. 17 is a schematic-block diagram illustration of the cursor logic
circuitry illustrated in FIG. 14;
FIGS. 18a through 18i are waveforms useful in describing both single and
dual column operation;
FIGS. 19a through 19p are waveforms useful in describing portions of the
circuitry employed herein;
FIG. 20 is a schematic illustration of a pixel matrix;
FIGS. 21a, b, and c are graphical illustrations showing images formed on
the video display;
FIGS. 22a, b, and c are similar to that of FIGS. 21a, b and c but showing a
different combination of graphical images formed on the video display;
FIGS. 23a, b, and c are similar to those of FIGS. 21a, b, c and 22a, b, and
c but showing a different combination of graphical images formed on the
video display;
FIG. 24 is a schematic-block diagram illustration of the direct memory
access circuitry;
FIGS. 25a through 25m are waveforms useful in describing the circuitry of
FIG. 24; and,
FIGS. 26a through 26p are waveforms useful in describing the circuitry of
FIG. 24.
DETAILED DESCRIPTION
General Description
Reference is now made to the drawings wherein the showings are for purposes
of illustrating a preferred embodiment of the invention only and not for
purposes of limiting same.
FIG. 1 is a generalized block diagram illustrating a system to which the
present invention applies. Here there is illustrated a host computer HC
which, for example, may take the form of a PDP-11/35 computer with 64K
words of memory obtained from Digital Equipment Corporation. Associated
with the host computer is a large data base storage DBS and which may take
the form of disc files, such as two 2.4 million byte moving head discs.
The system disclosed in FIG. 1 also includes data input sources DIS which
may include, for example, wire lines from which UPI and AP stories are
obtained. Other input sources may include a paper tape source or an
optical (OCR) reader or a modem.
These data input sources provide stories and the like which may be inputted
under the control of the host computer HC by way a system multiplexer MX
for storage in the appropriate file at the data base storage DBS. Also
associated with the system is a plurality of editing terminals T1, T2,
through TN. Each editing terminal takes the form of a processor driven
video display terminal having a keyboard and a display screen. With such a
system, a news writer may use an editing terminal to create a story which
is displayed on the display screen. Once the writer is satisfied with the
story, he will actuate a send key and coded data representative of the
story will be supplied through the system multiplexer MX to the host
computer HC which will then store the story in a particular storage
location at the data base storage DBS for subsequent retrieval. Other
stories may be obtained from the data input sources DIS and routed by host
computer HC for storage in the data base storage DBS.
An editor, through the use of his editing terminal, may call up a story
entered into the data base storage from either one of his writers or from
one of the data input sources DIS. In this case, the proper keys on the
terminal's keyboard will be actuated and the story will be retrieved from
the data base storage and supplied under the control of the host computer
HC to the terminal requesting the story. The editor will now view the
story on his display screen and make whatever editing corrections he
requires, using the proper editing controls on the keyboard. Once the
edited story has been completed, the editor will actuate a send key on the
keyboard and the edited story will now be stored at the data base storage
but in a different location from the unedited story. An edited story
located at the data base storage will, under computer control, be supplied
to one or more of a plurality of data output devices DOD. Suitable output
devices known in the art include typesetters, papertape punches, printers
and modems. Systems of the nature described thus far are well known in the
art and have been installed in several newspaper facilities. No further
description of the overall system will be presented herein unless it has
particular concern with respect to the invention.
Video Display Terminal (General)
Reference is now made to FIG. 2 which illustrates a block diagram of a
video display terminal in accordance with the present invention and which
may be used in a system such as that illustrated in FIG. 1. The terminal T
of FIG. 2 is a processor-driven terminal employing a common bus structure.
The bus structure may be divided into an address bus AB, a data bus DB and
a control bus CB. By way of example only, the address bus may be a 16 bit
bus and the data bus may be an 8 bit bus. An interface to the host
computer HC is obtained with an input/output control IO. The input/output
control IO, in a conventional manner, communicates with the address bus,
the data bus and the control bus. Also connected to the common bus is the
central processing unit CPU, a bootstrap memory BS, a main random access
memory M, a keyboard KB, and a video display control VDC which includes a
direct memory access circuit DMA and a character generator CG.
The character generator communicates in a conventional fashion with a
display means in the form of a cathode ray tube CRT by way of a suitable
video amplifier VA and vertical and horizontal deflection amplifying
circuitry DA. A power supply circuit PS is activated upon closure of a
switch SW to receive A.C. line power. The power supply provides the
various DC level signals required by the circuitry as well as an output
which carries an AC line signal to a power line synchronization generator
PLS. For example, the AC line signal may be a six volt RMS signal. The
power line synchronization generator PLS provides output pulses that are
synchronized to the AC line signal, as shown by the waveforms in FIG. 2,
and this provides output pulses to the character generator to provide a
command for start of frame (STRTFR). A control output is also obtained
from the power supply circuit PS to provide a power-up signal (PWRURS).
A general description of the operation of the terminal is now presented. As
the editor or writer commences use of the terminal he will actuate a
power-on switch SW which will raise the power-up line PRWUPS. This is
routed to the control bus and from there to the processor CPU. This
causes, under program control, an interrogation of the bootstrap memory BS
which then supplies to the data bus DB some data in the form of a terminal
identification. The bootstrap memory is a programmable read only memory or
other non-volatile storage facility. The terminal identification is
supplied by the data bus DB to the host computer HC by way of the
input/output control IO. The host computer will now download program
instructions to the terminal for storage in the main memory M. The
terminal is now programmed to perform its intended operation, i.e., such
as a sports editor terminal. In such case, the editor will now employ the
keyboard KB for transmitting a code to the host computer to ask for a
particular story. Under the program control, the information provided by
the keyboard KB will appear on the data bus line and then be transmitted
by way of the input output control IO to the host computer. The host
computer will then retrieve the requested story from the data base storage
DBS and supply the story to the terminal. Under program control, the
terminal will route the story for storage in the main memory M. At this
point, the main memory M will store both program instructions for internal
operation of the processor as well as the data representing the text to be
displayed on the CRT.
The data characters stored in main memory are read and routed to the
character generator where the data characters are decoded to obtain the
proper video dot pattern for display on the CRT screen. The main memory is
accessed under the control of a direct memory access control circuit DMA.
This circuit operates in response to control signals from the character
generator CG and fetches data from the memory with the data then being
supplied to the character generator by way of a data bus DB. The data
received by the character generator is then employed to provide video
patterns representative of data characters for display on the cathode ray
tube CRT.
Before explaining the various circuits in detail, the following discussion
is presented with respect to various blocks illustrated in FIG. 2. For
example, the processor CPU serves to execute programs which are downloaded
to the main memory M. The processor may take any convenient form of
microprocessor such as the Intel Microprocessor Model 8080 and which is
described in detail in that company's User's Manual 98-153C dated
September, 1975. The reader is referenced to that manual for a complete
discussion of the processor. Basically, it takes the form of an 8 bit
machine having an 8 bit directional data bus, a 16 bit address bus, and
has addressing capability for up to 64,000 8 bit bytes of memory.
The bootstrap memory BS includes a programmable read only memory (PROM).
This is a non-volatile storage of a bootstrap program which, when executed
by the CPU during the power-up sequence of the terminal, causes
transmission of a message by way of the data bus DB to the host computer
HC requesting a download of the terminal control program. The downloaded
program is stored in the terminal's main memory M which includes storage
capacity for the text data to be displayed on the CRT as well as working
memory for use by the CPU. The main memory M may take the form of a 16K 8
bit word random access memory.
The character generator converts the received data into a serial video
stream which is applied by the video amplifier VA to control the
blank/unblank operation of the CRT. A full screen of display may include,
for example, 27 lines of 72 characters each. Preferably, a T.V. raster
scan technique is employed and which incorporates a vertical raster. The
character generator provides to the video amplifier a serial bit stream
which corresponds to vertical display raster columns. As will be brought
out in greater detail hereinafter, each character is displayed within a
12.times.15 dot matrix. The dot matrix hereinafter will be referred to in
terms of pixels (picture elements). The normal character is 11 pixels wide
and with one pixel intercolumn spacing 12 vertical raster scans are
required for the display of each of the 72 columns of characters on the
screen. The depth of a character field is potentially 15 pixels long. Each
data character represenative of text information is accompanied by an
additional 8 bit word of information which hereinafter is referred to as
an enhancement character. The enhancement character causes video
modification of the display of the data character. Consequently, the video
stream as sent to the video amplifier is enhanced or altered by the
character generator as required to achieve the proper modified display.
The keyboard KB includes a plurality of text entry keys and various
indicator lights and a keyboard layout is illustrated in FIG. 3. There may
be as many as 105 key switches located on the keyboard and its interfaces
to the CPU such that presentation of the pressed key codes to the CPU is
on an interrupt basis in a manner well known in the art. Most of the keys
are conventional in the art and only mention here will be made. Thus, the
main keyboard includes a group of text entry keys for use in entering
alphanumeric characters. In addition, here are keys to provide shift and
shift lock, double and triple shift. The keyboard also includes a
pluraltiy of editorial mark-up keys to provide such functions as begin and
end command, subformat, new paragraph, flush codes for flushing left,
center and right, define block (which is a key that inserts a block marker
on the screen and advances the cursor to the next character position).
There are also several text display control function keys to provide
certain control functions. These include a clear key 10, scroll-up key 12,
scroll-down key 14, a page-up key 16, and a page-down key 18. The clear
key 10 is used by the operator when he desires to destructively clear all
text displayed on the screen from memory. The scroll-up and scroll-down
keys 12 and 14 permit the operator to move the active display window on a
line basis.
Momentary depression of the scroll up (down) key causes the display text to
move up (down) one line on the screen, thereby forcing a line from the top
(bottom) of the display to be transmitted to the host computer for storage
to allow room for the next contiguous line to be displayed on the bottom
(top) line which is received from the data base storage. If the scroll key
is held down then the scroll will repeat at a rate of, for example, 10
lines per second until released. When in the dual screen mode, only the
text which contains the cursor will be permitted to scroll. The page-up
key 16 and the page-down key 18 when actuated cause a page-up (down)
operation which causes the next screen (previous) full of text to be
displayed.
The cursor control keys are shown on the left side of the keyboard and
include a move left key 20, move right key 22, move up key 24, and move
down key 26. Each key includes an arrow designating the direction of
movement. The cursor controls permit the cursor to be positioned at any
one of the possible display character locations on the screen. A momentary
actuation of one of the cursor control keys causes a one character
position movement of the cursor in the appropriate direction. The
alternate cursor key 30 is used when the terminal is in a dual screen mode
of operation. For example, during the dual screen operation in which two
different stories in two side-by-side columns of text are displayed,
editing functions and the like can take place only in that portion in
which the cursor is located. Actuation of the alternate cursor key 30
causes the cursor to move from one column to the other column. Actuation
of the home key 32 causes the cursor to move to its home position,
normally in the upper left hand corner of the text being displayed. The
next line key 34 acts as a carriage return on a typewriter in that it
causes the cursor to be moved from its current position to the first
character position on the line immediately below.
The command keys shown on the upper portion of the keyboard are used in
conjunction with a shift key such as key 36 or 38. For example, when the
italic-bold key 40 is actuated in the unshift mode it will cause a bold
video modification to be used to represent bold type face. In the shifted
mode, actuation of the key 40 will cause an italic video modification to
be used to represent italic type face. Similarly, in the unshifted mode,
actuation of key 42 will cause a video modifier of strike-through to be
applied to characters on the display. In the shifted mode actuation of key
42 will cause an underline video modifier. Additional command keys include
a cross hatch command key 44 which when actuated will cause a cross hatch
enhancement on the character display. Actuation of key 46 will cause a
dotted underline enhancement. Actuation of key 48 will cause a blink
enhancement to cause the data character at that location to blink.
Similarly, actuation of key 50 will cause a video inversion enhancement.
These enhancements will all be described in greater detail hereinafter.
Actuation of any of these keys causes a unique 8 bit data word to appear
on the data bus and stored in an address location in the main memory and
it is used by the character generator CG for displaying the appropriate
character. The manner in which the character generator and direct memory
access circuit operate will be described in detail hereinafter.
A dual column key 49 is used to select and deselect the dual column display
mode of a single item. The display modes may not be switched during active
display of an item, depression of the dual column key with a take or
directory on the screen will have no affect. When the dual column key is
struck when the terminal is inactive, the terminal switches into the dual
column display mode (two columns of up to 27 lines of up to 35 characters
per line), illuminates a dual column indicator, clears the screen and
homes the cursor. If the dual column mode is active and the operator wants
to switch to normal display mode, the operator ends any active display
item and depresses the dual column key again which extinguishes the
indicator and reverts the terminal to normal display mode.
When dual column mode is active, any directory or take which is called to
or begun on the terminal is displayed in two 35 character per line columns
with the first line (which may be text or header information) in the top
left column line. Subsequent thirty-five character lines fill the
remainder of the left hand column to the bottom of the screen and the
right hand column from the top of the screen to the bottom. Thus, the
bottom line of the left column is adjacent to (i.e., the line above) the
top line of the right column and they are so treated during any editing,
display or cursor manipulations.
The dual screen key 51 is used to select and deselect the dual screen
display mode, which permits simultaneous display of two takes in a
vertically split display manner. Since display modes may not be changed
during active display of an item, depression of the dual screen key with a
take or directory on the screen will have no effect. When the dual screen
key is struck when the terminal is inactive, the terminal switches into
the dual screen mode, clears the screen, homes the cursor (upper left) and
illuminates the dual screen display indicator. The next depression of this
key when there are no items actively displayed will revert the display to
normal mode and extinguish the indicator. When the editor fetches the
first item to be displayed in active dual screen mode it is placed on the
left half of the screen with the line lengths no greater than 35
characters, with the cursor placed in the home (upper left hand corner)
position on that take. Protected text in head lines and formats is broken
at the line length without regard for word wrapping in order to preserve
the integrity of the protected format. Once the left hand item is thus
activated, the editor may use the alternate take key to activate the right
hand column so that he may fetch or begin a second time. He may then
proceed to control and edit the text in either column. The take in which
the cursor is located is defined as being "active". All normal text and
function keyboarding done by the editor is in the active take. Additional
command keys include a send command key 52 which is used to initiate
transmission of data to the host computer HC.
Processor
The central processing unit CPU is shown in greater detail in FIG. 4. This
is a general purpose processor and may take the form of an Intel 8080A
processor. This processor and its interfacing with the common bus may be
understood by reference to Intel's System User's Manual 98-153C dated
September, 1975. However, to facilitate an understanding of the CPU,
reference should now be made to Table I which describes the function of
the CPU inputs and outputs. Several of the descriptions refer to internal
timing periods.
TABLE I
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A.sub.15 A.sub.0
(output three-state)
ADDRESS BUS; the address bus provides the address to
memory (up to 64K 8-bit words) or denotes the I/O device
number for up to 256 input and 256 output devices. A.sub.0
is the least significant address bit.
D.sub.7 -D.sub.0 (input/output three-state)
DATA BUS; the data bus provides bi-directional
communication between the CPU, memory, and I/O devices
for instructions and data transfers. Also, during the
first clock cycle of each machine cycle, the CPU outputs
a status word on the data bus that describes the current
machine cycle. D.sub.0 is the least significant bit.
SYNC (output)
SYNCHRONIZING SIGNAL; the SYNC pin provides a signal
to indicate the beginning of each machine cycle.
DBIN (output)
DATA BUS IN; the DBIN signal indicates to external
circuits that the data bus is in the input mode. This
signal is used to enable the gating of data onto the data
bus from memory or I/O.
READY (input)
READY; the READY signal indicates to the CPU that valid
memory or input data is available on the data bus. This
signal is used to synchronize the CPU with slower memory
of I/O devices. If after sending an address out the CPU
does not receive a READY input, the CPU will enter a WAIT
state for as long as the READY line is low. READY can
also be used to single step the CPU.
WAIT (output)
WAIT, the WAIT signal acknowledges that the CPU is in a
WAIT state.
WR output
WRITE, the WR signal is used for memory WRITE or I/O
output control. The data on the data bus is stable while
the WR signal is low (WR = 0).
HOLD (input)
HOLD; the HOLD signal requests the CPU to enter the HOLD
state. The HOLD state allows an external device to gain
control of the CPU address and data bus as soon as the
CPU has completed its use of these buses for the current
machine cycle. It is recognized under the following
conditions:
the CPU is in the HALT state.
the CPU is in the T2 or TW state and the READY signal is
active.
As a result of entering the HOLD state the CPU ADDRESS
BUS (A.sub.15 -A.sub.0) and DATA BUS (D.sub.7 -D.sub.0) will be in
their high impedance state. the CPU acknowledges its
state with the HOLD ACKNOWLEDGE (HLDA) pin.
HLDA (output)
HOLD ACKNOWLEDGE: the HLDA signal appear in response to
the HOLD signal and indicates that the data and address
bus will go to the high impedance state. The HLDA signal
begins at:
T3 for READ memory or input.
The Clock Period following T3 for WRITE memory or
OUTPUT operation.
In either case, the HLDA signal appears after the rising
edges of 0.sub.1 and high impedance occurs after the rising
edge of 0.sub.2.
INTE (output)
INTERRUPT ENABLE; indicates the contents of the internal
interrupt enable flip/flop. This flip/flop may be set or -reset by the
Enable and Disable Interrupt instructions
and inhibits interrupts from being accepted by the CPU
when it is reset. It is automatically reset (disabling
further interrupts) at time T1 of the instructions fetch
cycle (M1) when an interrput is accepted and is also
reset by the RESET signal.
INT (input)
INTERRUPT REQUEST; the CPU recognizes an interrupt
request on this line at the end of the current
instruction or while halted. If the CPU is in the HOLD
state or if the Interrupt Enable flip/flop is reset it
will not honor the request.
RESET (input)
RESET; while the RESET signal is activated, the content
of the program counter is cleared. After RESET, the
program will start at location 0 in memory. The INTE and
HLDA flip/flops are also reset. Note that the flags,
accumulator, stack pointer, and registers are not cleared.
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From FIG. 4, it will be noted that the various inputs such as RESET, READY,
discussed in Table I are found on the appropriate inputs and outputs to
the CPU. The interface to support the CPU includes a CPU timing and
control circuit 60, address buffers 62, data buffers 64 and a system
control 66. These are all conventional in the art and are components
typically employed in conjunction with supporting an Intel 8080 CPU in its
interface with the common bus structure. Before describing these
components, reference should be made to Table II. This is a signal
mnemonic dictionary which is useful not only for an understanding of the
signal mnemonics shown in FIG. 4, but those to be used in the remaining
figures herein.
TABLE II
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A** CPU ADDRESS BIT ** (**00 through 15)
AB** ADDRESS BOT ** (** 00 through 15)
ACLSYN AC LINE SYNC
BEN BUS ENABLE
BLINKC BLINK CLOCK
BLKDEC BLANK (INHIBIT) DECODER
BLNKV1 BLANK VIDEO 1 (SLOW BLANKING)
BLNK2 BLANK VIDEO 2 (FAST BLANKING)
BUSEN BUS ENABLE (CPU IN HOLD MODE)
CCOL** CHARACTER COLUMN ** (**=34,62, etc.)
CCOLB* CHARACTER COLUMN CTR BIT * (*=0 through
6)
CE* CHIP ENABLE * (*=0 through 3)
CEW CHIP ENABLE WRITE
CGDFET CHARACTER GEN DATA FETCH MEMORY CYCLE
CHCOD* CHARACTER DATA CODE (LATCHED) BIT * (*=
0 through 7)
CHDAT* CHARACTER DATA * (*=0 through 7)
CLK INT CLOCK INTERRUPT REGISTER
CNTRAC COUNT REFRESH ADDRESS AND ACCESS CNTR
CNTVAC COUNT VECTOR ADDRESS CNTR
CNTVTA COUNTER VECTOR TABLE ADDRESS CNTR
CS* CHIP SELECT * (*=0 through 3)
CTVRAC COUNT VECTOR RAM ADDRESS CNTR
D* CPU DATA BUS BIT * (*=0 through 7)
DAFEMD DMA IN DATA FETCH MODE
DAOVEF DATA OR VECTOR FETCH MODE
DATAFE DATA (OR VECTOR) FETCH MEMORY CYCLE
DATFE2 SECOND DATA (OR VECTOR) FETCH
DB* DATA BUS * (*=0 through 7)
DBIN DATA BUS INPUT (TO CPU) MODE
DCFEVE DUAL COLUMN FETCH VECTORS
DFVACR DATA FETCH VECTOR ADDRESS CNTR LOAD
DI* RAM DATA INPUT BIT * (*=0 through 7)
DMACT DMA ACTIVE
DMAENA DMA ENABLED BY CPU
DO* RAM DATA OUTPUT BIT * (*=0 through 7)
DUALCO DUAL COLUMN MODE
DVAL DATA VALID FROM MEMORY
DVALAX DATA VALID (DOUBLE BUFFERED)
DVALAXX DATA VALID (BUFFERED)
ENAVAC ENABLE VECTOR ADDRESS CNTR TO BUS
ENAVTA ENABLE VECTOR TABLE ADDRESS TO BUS
FEDATA FETCH DATA
H. CTR HORIZONTAL CENTER (BUFFERED)
HCENTR HORIZONTAL CENTER
HOLD HOLD CPU
HRETRC HORIZONTAL RETRACE
HRT HORIZONTAL RETRACE
HWCURS CURSO VIDEO ENABLE
I/OR I/O READ
I/OW I/O WRITE
IMRCLK INTERRUPT MASK REG CLOCK
INT INTERRUPT CPU
INT* INTERRUPT * (*=0 through 7)
INTACK INTERRUPT ACKNOWLEDGE
INTE INTERRUPT ENABLE
KB* KEYBOARD DATA BIT * (*=0 through 7)
LDBYT1 LOAD VECTOR BYTE 1
LDBYT2 LOAD VECTOR BYTE 2
LDO LOAD RAM DATA OUTPUT REG
LINE ** LINE ** (**=01, 32, etc.)
LINE SYNC
AC LINE SYNC
LINEB* LINE BIT * (*=0 through 4)
LODVAC LOAD VECTOR ADDRESS COUNTER
MC MASTER CLEAR
MCSWITCH
MASTER CLEAR SWITCH
EMECYC MEMORY CYCLE (ENA MEMRD)
MEMRD MEMORY READ CYCLE
MEMW MEMORY WRITE CYCLE
MSTCLR MASTER CLEAR (BUFFERED)
PIXL** PIXEL DATA BIT ** (**=01 through 16)
PULLUP* PULLUP BUX * (*=A,B,C)
PWRURS POWER UP RESET
PXCT01 PIXEL COUNT 01
PXCT17 PIXEL COUNT 17
PXCT19 PIXEL COUNT 19
PX0910 PIXEL COUNT 09 and 10
PX1617 PIXEL COUNT 16 and 17
PX1819 PIXEL COUNT 18 and 19
PX1819 PIXEL COUNT 18 and 19
RDBUFA READ BUFFER "A"
RDBUFF READ NEXT BUFFER RAM ADDRESS
READY CPU READY
RSTVTA RESET VECTOR TABLE ADDRESS COUNTER
RSVRAC RESET VECTOR RAM ADDRESS COUNTER
SELBUS SELECT COMMON BUS TO VECTOR RAM INPUT
SST-1 STATUS REG STROBE 1
SST-2 STATUS REG STROKE 2
STRKB* STROKE BIT * (*=0 through 3)
STRK01 STROKE 01
STRTFE START (VECTOR) FETCH
STRTFR START OF FRAME
S1 KEYBOARD STROBE 1 (UNSHIFT AND SHIFT)
S2 KEYBOARD STROBE 2 (SHIFT 2 and 3)
TIMEQA DMA TIMING SHIFT REG Q-SUB-A OUTPUT
TIMEQ DMA TIMING SHIFT REG Q-SUB-D OUTPUT
UNBLNK UNBLANK CRT
V-S CLX VERTICAL SYNCH SHIFT REG CLOCK
VACB** VECTOR ADDRESS CNTR BIT ** (**=0 through)
15)
VECB** VECTOR RAM OUTPUT DATA BIT ** (**=0
through 15)
VEFEMD DMA IN VECTOR FETCH MODE
VESYNC VERTICAL SYNC
VID EN VIDEO ENABLE (PROTECTIVE BLANKING)
VRID** VECTOR RAM INPUT DATA BIS ** (**=0
through 15)
VRT VERTICAL RETRACE
V1 VIDEO LEVEL 1 (LIGHT)
V2 VIDEO LEVEL 2 (NORMAL)
WE WRITE ENABLE
WR WRITE STROBE
WRTVEC WRITE DATA INTO VECTOR RAM
OC CPU CLOCK
OA PIXEL CLOCK
OB BLANK/UNBLANK CLOCK
__________________________________________________________________________
As indicated by the mnemonics shown in FIG. 4, the timing and control
circuit 60 receives various signals from the control bus such as master
clear and provides basic timing reference with the signals required by the
CPU. The timing and control circuit is conventional in the art and may,
for example, comprise a modified Johnson counter. The address buffer
provides buffering of the 16 bit AB.sub.0 to AB.sub.15 address bits from
the CPU to the address bus AB. The data buffer 64 provides buffering for
the 8 bit DB.sub.0 to DB.sub.7 data bits going from the CPU to the data
bus DB or from the data bus DB to the CPU. The system control 66 provides
the various system commands under processor control, and includes such
system commands as MEMW. These are all transmitted to the control bus CB.
Bootstrap
Also shown in FIG. 4 is the interfacing of the bootstrap memory BS with the
common bus. Basically, an address buffer 68 receives a 16 bit address from
the addr | | |
