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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data processing systems and more
specifically to a writeable control store for use in the processor of a
data processing system.
2. Description of the Prior Art
In many data processing systems, and especially in smaller, economical data
processing systems, the internal operations of the processor are
controlled by the execution of instructions stored in an internal control
store. In such systems, these instructions are typically stored in a read
only memory (ROM) of a limited storage capacity. These ROMs are typically
programmed at the factory and are not alterable in the field.
However, many systems are provided with additional control store
capabilities typically in the form of an option which may be programmed in
the field for a particular application. These control stores are typically
comprised of a random access memory (RAM) which may be loaded or written
with data used to control the operation of the processor.
Typically, the loading or writing of such a control store is controlled by
either the main control store (ROM) or the extendable or writeable control
store itself. Both of these methods are uneconomical and may degrade the
performance of the processor by utilizing additional time to complete the
actual loading of the writeable control store.
Utilization of the primary control store or ROM to control data transfers
to and from the writeable control store requires the use of additional
storage locations within the ROM which must be dedicated for this purpose.
In a smaller economical system, these additional storage locations may not
be available or may require the sacrifice of additional capabilities of
the machine. This is a particularly difficult burden because these storage
locations may not even be utilized, since the variable control store is
typically provided as an option and, may not be used in many cases.
Additionally, the length of the instruction required to control the data
transfers to and from the writeable control store will typically be
substantially less in size than the length of the instruction normally
utilized to control the operation of the machine. Thus, by using the
primary control store, storage locations for substantially longer words
must be used even though the capacity of each is only partially utilized.
Utilization of the writeable control store to control data transfers to and
from itself is uneconomical for the same reasons specified above for the
primary control store ROM. Additionally, in most systems, this will also
degrade the performance of the machine in that at least one additional
machine cycle will be required to complete the loading of the WCS unit.
Specifically, a machine cycle will be required to access the instruction
utilized to control the transfer and an additional machine cycle will be
required to actually complete the loading or writing operation.
SUMMARY OF THE INVENTION
The present invention overcomes the aforementioned difficulties with the
prior art by providing a writeable control store which can control such
data transfers to and from WCS array both economically and in a minimal
amount of time.
Specifically, a secondary control store is provided in the writeable
control store to control the operation of the processor during such times
as data is being transferred to the writeable control store. The secondary
control store is programmed with a plurality of instructions grouped
together in routines and utilized to control such data transfers. The
secondary control store is preferably enabled by one of several
instructions stored in the main control store or in the WCS array or RAM
store which will address the first instruction in one of the routines
stored in the secondary control store and transfer control of the
processor to the secondary control store. Upon completion of the execution
of the routine, control is returned to the RAM in the writeable control
store.
The capacity of the storage locations of the secondary control store of the
present invention may be substantially smaller, with respect to the number
of bits per storage location, than the primary control store (ROM) or the
RAM in the writeable control store. The number of storage locations in the
primary control store required in the prior art techniques for enabling
the transfer of data to and from the writeable control store is
substantially reduced by use of the present invention. Additionally, the
execution time of any instruction requiring a transfer to the writeable
control store under the control of the secondary control store means can
be performed at normal machine cycle rate. Thus, additional machine cycles
will not be required to complete the loading of storage locations in the
writeable control store.
Additionally, use of the present invention in conjunction with a writeable
control store permits the writeable control store to be economically used
as both a control store and an extension or local store for data without
degrading the performance of the processor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block-schematic diagram of a data processing system depicting,
in particular, a processor incorporating the present invention.
FIG. 2a is a block diagram depicting a clock circuit used to generate clock
pulses for use by the processor in FIG. 1.
FIG. 2b is a timing diagram depicting the sequence of clock pulses
generated by the clock circuit of FIG. 2a.
FIG. 3 is a representative illustration of the bus control field of
information contained in each processor instruction for controlling
transfers of data over the internal data busses of the processor in FIG.
1.
FIG. 4 is an illustration of a control store register utilized to control
the selection of storage devices within the units of the processor in FIG.
1 for data transfers over the data busses of the processor in FIG. 1.
FIG. 5 is a block diagram of a writeable control store unit in the
processor of FIG. 1 depicting, in particular, the present invention for
controlling data transfers to the control store device of the writeable
control store unit.
CROSS REFERENCES TO RELATED PATENTS AND APPLICATIONS
The following U.S. Patents and U.S. Patent Applications, all of which are
assigned to the assignee of the present application are hereby
incorporated by reference: U.S. Pat. No. 3,710,324 entitled "Data
Processing System" in the name of John B. Cohen, et al; U.S. Pat. No.
3,614,740 entitled "Data Processing System with Circuits for Transferring
Between Operating Routines, Interruption Routines, and Sub-Routines" in
the names of Bruce A. Delagi, et al; U.S. Pat. No. 3,614,741 entitled
"Data Processing System with Instruction Addresses Identifying One of a
Plurality of Registers including the Program Counter" in the names of
Harold L. McFarland, Jr., et al; and co-pending application Ser. No.
776,331 entitled "An Processor for a Data Processing System" in the names
of Charles H. Kaman, et al.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a block-schematic diagram of a data processing system
10 is shown which includes a processor 12 that incorporates the present
invention. In addition to the processor 12, the data processing system 10
includes a memory 16 and at least one peripheral device, such as
peripheral device 18, each of which is interconnected by a data bus 20.
The data bus 20 couples all address, data and control information between
the processor, the memory and the peripheral devices.
The processor 12 is comprised of a number of units, each of which is
connected between a Din bus 22 and Dout bus 24. The processor units, some
of which will be described in greater detail hereinafter, include a bus
control unit 26, for controlling the use of the data bus 20, a processor
memory unit 28 for storing data therein for quick retrieval by the
processor 12, a data path unit 30 for performing arithmetic and
manipulative operations on data, and a processor control unit 32 for
storing previously programmed instructions for controlling the operation
of the processor and utilized to fetch, interpret and execute the external
instructions typically stored in the memory device 16. The processor 12
also includes additional or optional units such as a floating point
processor unit (not shown) or a writeable control store unit (WCS) 33 for
storing additional instructions which may be used to control the operation
of the processor. Additionally, it should also be noted and understood at
this point that the configuration in FIG. 1 is exemplary and that other
configurations may be utilized which incorporate the present invention.
Still referring to FIG. 1, and, in particular, to the processor control
unit 32, a control store 34, typically a ROM (read-only-memory), is shown
therein which is preprogrammed with a plurality of processor instructions
or microwords (hereinafter referred to as .mu.-words) which are used to
control the processor 12 for specific intervals of time. In the preferred
embodiment shown in FIG. 1, the .mu.-word is comprised of a multiple
binary bit word which is divided into a number of fields. The
interpretation of the various fields by the processor 12 dictates what
action will take place therein.
Each .mu.-word is stored within the control store 34 at an addressable
location. The address of the desired .mu.-word is placed on the next
.mu.-word address bus (NUA) 36 and at the beginning of the next processor
timing cycle or microcycle (hereafter .mu.-cycle) the contents of that
location are read from the control store 34 and loaded into the microbus
register 38.
At this point, a brief mention of the processor timing should be made since
timing is a critical part of any data processing system. Referring to FIG.
2a, a timing generator 44, which in the embodiment of the processor 12
depicted in FIG. 1 is located within the bus control unit 26, is comprised
of a pulse generator 106 coupled to a clock logic circuit 108. The pulse
generator 106 produces a uniform series of electrical signals. The clock
logic circuit in turn generates, in response to these signals, the
sequential pulse streams (P1, P2, P3 and P4) depicted in FIG. 2b.
At the beginning of each .mu.-cycle, a pulse P1 is coupled to the control
store 34 which causes the contents at the address indicated on the NUA bus
36 to be read and loaded into the microbus register 38. The .mu.-cycle,
which is defined for the purposes of the processor 12 utilized in the
preferred embodiment, as the time between successive loadings of the
register 38 (i.e. between successive P1 clock pulses), may range from
nanoseconds to microseconds depending upon the performance characteristics
of the machine. The remaining pulses (P2, P3 and P4) in each .mu.-cycle
are used to control the timing of events which the .mu.-word has
specified, such as, for example, loading of registers, transfer of
information performing arithmetic operations in the data path 30, etc.
Referring again to FIG. 1, the contents of register 38 are coupled
throughout the processor 12 via the .mu.-word bus 40 for interpretation
and implementation by the processor 12. Various portions or fields of the
.mu.-word are coupled to a microcontrol (UCON) register 42 and the address
and branching circuit 44.
As previously indicated the .mu.-word is comprised of numerous binary bits
which are grouped into fields for the purposes of interpretation by the
processor 12. For example, a group of bits referred to as the micropointer
field (UPF), contains the address of the next .mu.-word to be addressed in
the control store 34 since the processor 12 in FIG. 1 utilizes the
technique of addressing the next .mu.-word for execution commonly referred
to as chained-sequencing addressing.
The .mu.-word also contains a 6-bit field called the micro branching field
(UBF) which designates branch tests to be performed within the processor
12 during a .mu.-cycle. Both the UPF and the UBR fields are coupled to the
address and branching circuit 44. Branch tests are utilized to alter the
address of the next .mu.-word if certain conditions, specified by the
branch field (UBF), exist. The contents of certain bit locations in
designated registers throughout the processor 12 which have particular
significance with respect to the state of the processor are coupled to a
logic circuit (not shown), typically a multiplexor, in the address and
branching circuit 44. The UBF field, which is coupled to this logic
circuit, selects certain of these information bits for logical
combination, typically ORing, with the low order bits of the UPF field. If
the conditions tested for by the UPF field are present, the UPF field is
altered in response thereto, and the result is coupled to the NUA bus 36
for selecting the next .mu.-word.
Several other fields are also included in the .mu.-word. These include a
clock field which designates which of certain devices are to be clocked
and at what point in the .mu.-cycle they are to be clocked at; a bus
control field, which indicates whether or not a transfer of data or
control information is to be performed between units in the processor 12
or between the processor 12 and a peripheral device connected to the data
bus 20; and a data path function field which controls the operation of the
data path 30.
Some of the fields in the .mu.-word, for example, the data path function
field, will be interpreted differently depending on the processor
operation specified by the .mu.-word. More particularly, if the function
specified by the .mu.-word does not involve a data path operation, then
the data path function field may be used for other purposes.
Several other registers and circuits are also contained in the processor
control unit 32 depicted in FIG. 1. These include an instruction register
(IR) 46, which is used to receive and store general or main instructions
fetched by the processor unit 12 from the data path 30, typically
originating in the memory 16 or peripheral 18 for interpretation and
execution. Coupled to the IR 46 is an instruction register decode circuit
48 which decodes the contents of IR 46. The output of the decode circuit
48 is coupled to the address and branching circuit 44 such that the UPF
field is altered if necessary and the appropriate program starting address
is coupled to the NUA bus 36.
Four general purpose registers, the emit register 50, the processor status
word register (PSW) 52, the floating point status register (FPS) 54, and
the program micropointer (UPP) register 56, are used, under the control of
the UCON register 42, to store certain information during the execution of
programs by the processor 12. For example, the emit register 50 is used to
store an entire field in the .mu.-word which may be used as data by the
data path 30 at a later time. The bits comprising this field are situated
in the same location within the .mu.-word that would ordinarily comprise
the datapath function field because a datapath function will not be
specified in such a .mu.-word. The PSW register 52 is used to perform the
same function as the Status Register 59 described in aforementioned U.S.
Pat. No. 3,710,324. This register contains such information as the present
mode of operation of the processing unit, the previous mode of operation,
the priority level at which the processor is operating, and the condition
codes, all of which are described in U.S. Pat. No. 3,710,324.
The FPS register 54 is utilized to store status information similar to the
PSW register 52 when an optional floating point processor is coupled to
the processor unit 12, and the UPp register 56 is utilized to track the
.mu.-word so that, if microroutine is interrupted, the address of the last
.mu.-word before the interruption will be stored therein.
Lastly, the processor control unit 32 in FIG. 1 includes a box multiplexor
circuit 58 which is utilized under the control of the UCON register 42 to
selectively couple the contents of one of the four status registers, 50,
52, 54 and 56, to the Din Bus 22. This device, along with the other box
multiplexors disposed in the other units of the processor 12, will be
described in greater detail hereinafter.
The data path unit 30 contains various holding registers, storage
locations, logic circuitry and an arithmetic logic unit (ALU) which are
used to perform the data manipulations within the processor 12. I
particular, the data path 30 shown in FIG. 1 contains three scratch pads,
60, 62 and 64. The A & B scratch pads, 60 and 62, are general purpose
scratch pads and are the primary storage location for data which will be
used by the data path 30 in the execution of a program. The C scratch pad,
64, is a special purpose scratch pad which is used by the data path 30 to
store error log information, constants often used by the data path in its
operation and to initially store all data coupled into the data path 30.
More specifically, a special register, MD, within the C scratch pad 64 is
loaded via the Din multiplexor 85 with any data or control information
coupled on to the Din bus 22 except general instructions.
The A and B scratch pads, 60 and 62, have certain storage locations therein
reserved for the general purpose registers described in U.S. Pat. No.
3,710,324. For example, these include a program counter register, which is
sequencially incremented to indicate the address of the next general or
special instruction which the processor 12 will fetch, interpret and
execute and a stack pointer register which points to an address in a
section of memory reserved as stacks and where the contents of the program
counter register and the FPS Register 52 for various microroutines in the
processor control unit 32 may be stored for later reference when the
processor 12 is interrupted, for example, by an external peripheral device
requesting service therefrom.
The ALU 66, which performs the arithmetic and logical data manipulations in
the processor 12 has two inputs thereto, an A input 68 and a B input 70.
The A input 68 has coupled thereto the outputs from the A scratch pad
registers 60, the shift tree 71, and a shift register 72. Coupled to the B
input 70 are the outputs from the B scratch pad registers 62 and the C
scratch pad registers 64. The ALU 66 performs the operations specified by
the .mu.-word on the data which is coupled to it on the A and B inputs 68
and 70, respectively. These operations include adding, subtracting,
ANDing, ORing, incrementing, decrementing, etc.
The D Register 74 and the shift register 72 are holding registers which are
coupled to the output of the ALU 66. The D register 74 may be written with
the output of the ALU 66 and/or read from during any .mu.-cycle. The
contents of the D register may be directed to a number of locations by the
.mu.-word, such as other locations in the data path 30, other units in the
processor 12, and external peripheral devices coupled to the data bus 20.
The shift register 72 is a register into which the output from the ALU 66
may be stored and shifted one bit to the left or right. Additionally, the
shift register may be used for other functions, such as a temporary
holding register which may be used to provide data to the A input of the
ALU 66 in subsequent operations.
The shift tree 71 performs various operations on the data store in the
D-register 74 such as a single bit shift to the left, a multiple bit shift
to the right, sign extensions and byte swaps. Unlike, the shift register
72 and the D register 74, the shift tree 71 is a combinational logic
element which does not hold its output across subsequent .mu.-cycles.
Thus, the output of the shift tree 71 must be operated on by the ALU 66 in
the same .mu.-cycle that the output from the D-register 74 is modified.
The remaining elements of the data path unit 30 shown in FIG. 1 are a logic
gate 76 through which the contents of the D register are coupled to the
Dout bus 24, and a bus address register 78 coupled to the A input 68 of
the ALU 66 and into which the address of a location is loaded to or from
which data and/or control information will be transferred. This address
may include the address of any location within a peripheral device
connected to the data bus 20 or to a location within the memory unit 28.
As previously indicated, the data path function field of the .mu.-word
controls the operation of the data path 30. In particular, this field
indicates the location within the scratch pads which will be coupled to
the ALU 66, the function which the ALU 66 or the shift tree 71, if any,
will perform and the disposition of the resulting product from the ALU 66.
An additional field in the .mu.-word will control the loading, if any, of
the contents of the D register into a register in the A or B scratch pads.
The .mu.-word also controls the loading of the bus address register 78 and
any shifting operations performed by the shift register 72.
The principal data buses within the processor unit 12, Din 22 and Dout 24,
which interconnect the various units within the processor should be
discussed briefly at this time. In particular, the Dout bus 24 is the bus
over which the contents of the D register 74 are coupled to any unit
within the processor 12 or to the data bus 20 for coupling to a memory or
peripheral unit. Thus, the D register 74 is the source of all information
which is coupled onto the Dout bus 24.
The Din bus 22 is used to couple data and control information to the
datapath unit 30. All data appearing on the Din bus are coupled to a
general storage register MD within the C scratch pad of the data path unit
30 except for general instructions which, as earlier noted, are coupled to
IR 46. Thus, with the exception of general instructions, the data path
unit 30 is the destination of all information coupled on to the Din bus 22
in the preferred embodiment shown in FIG. 1.
The memory buffer unit 28 which includes a cache memory 83 used to store
data for quick retrieval by the processor 13 and the bus control unit 26,
which is utilized for controlling transfers of the data bus 20 are
described in greater detail in applicants copending application Ser. No.
776,331.
Referring to FIG. 3, a segment or field of the .mu.-word, the bus control
field, is illustrated which is used to control the transfer of information
over the Din bus 22 and the Dout bus 24. In particular, a D-cycle bit
distinguishes between a .mu.-word which requires use of the Din or Dout
busses as opposed to one that does not. Thus, for example, a binary one in
the D-cycle bit indicates that a transfer over one of these two busses is
required whereas a binary zero in this bit indicates that these busses
will not be used during the .mu.-cycle. The IN/OUT bit of the bus control
field is utilized by the processor 12 in conjunction with the D-cycle bit
to distinguish between internal and external operations over the Din and
Dout buses. For example, when the D cycle bit is a binary one and the
IN/OUT bit also has a value of binary one, then the .mu.-word has
specified an operation over the Din or Dout busses which is internal with
respect to the processor 12. However, a value of binary zero in the IN/OUT
bit in conjunction with a value of binary one in the D-cycle bit indicates
a transfer over the Din or Dout busses between the data path unit 30 and
an external memory or peripheral device coupled to the data bus 20. The
remaining bits of the bus control field are utilized to supply additional
information for controlling the Din and Dout busses such as, for example,
designating between the Din and Dout busses for the transfer of
information.
If the .mu.-word defines an internal processor transfer over the Din or
Dout bus (ie, the D-cycle and the IN/OUT bits both have a value of binary
one), control information in the .mu.-word relating to the interunit
transfer is stored in the UCON register 42. Specifically, as shown in FIG.
4, the loading of the UCON register 42 is controlled by an AND gate 150
having inputs coupled to the D-cycle bit and IN/OUT bit of the .mu.-word.
The portion of the .mu.-word typically reserved for the data path function
field is used as the data source for the UCON register 42 since a data
path operation will not take place in this .mu.-word.
The UCON register 42 stores a plurality of bits which are divided into two
fields; the select field and the control field. The select field is used
to designate which unit in the processor will communicate with the data
path 30. Thus, the number of bits comprising the select field is
determined by the number of units within the processor unit 12. More
particularly, the number of bits in the select field is at least equal to
the number of units coupled to the processor unit 12 in addition to the
data path 30. In the processor 12 depicted in FIG. 1 only one unit is
permitted to communicate with the data path 30 at one time. Thus, only one
bit within the select field of the UCON register 42 may have a value of
binary one at any one time, where a binary one is the value used to select
such a unit. It should be noted, however, that with the addition of
appropriate logic circuitry and/or .mu.-word bits more than one unit could
be selected in the select field of the UCON 42 at one time.
The control field of the information stored in the UCON 42 is used in
conjunction with the select field to provide additional control
information necessary to select a particular device, such as a register,
for communication with the data path unit 30. Referring again to FIG. 1,
and, in particular to the processor control unit 32, it can be seen that
the devices which communicate with the data path 30 over the Din bus 22
are coupled thereto through a multiplexor such as multiplexor 38. Although
not shown in FIG. 1, each unit may have more than one multiplexor and each
multiplexor may have several registers or other storage devices coupled to
the inputs thereof. Thus, the control field of the data stored in the UCON
register 42 is used (in continuation with logic circuitry not shown) to
select the multiplexor and the register or other storage device within the
selected unit for communication with the data path 30. Since the control
field of the UCON register is decoded in conjunction with the select field
and only one unit is selected at any one time, the same bits within the
control field may be utilized for selection of the various registers and
storage devices within all of the units of each unit within the processor
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