A digital-to-analogue converter which uses a technique of two-level quantization in order to generate a pulse density code signal which yields the analogue signal when filtered. Standard digital logic adders and registers are used in the conversion of PCM signals to the pulse density code. The adders and registers are arranged as a feedback loop in which an approximation signal capable of either a "high" or a "low" level is compared repetitively with a PCM signal and the difference is accumulated, but at the end of each operation the accumulated total is tested and the value of the approximation signal for the next cycle is chosen so as to reduce the accumulated total. The cycle period is set by a clock, and the approximation signal is the pulse density code signal. The noise spectrum of the pulse density code signal may be adjusted by the addition of an offset signal to the incoming PCM signal. The digital-to-analogue converter is suitable for use in converting linear PCM telephone speech signals into analogue signals.
A digital-to-analog converting device comprises a signal processing circuit supplied with a discrete digital signal x.sub.n at a time nT, where n is a natural number and T is a sampling period, for converting the discrete digital signal x.sub.n into a digital signal y.sub.n satisfying an equation ##EQU1## where N is a natural number greater than i, a digital-to-analog converter for converting the output digital signal y.sub.n of the signal processing circuit into an analog signal having a continuous amplitude, and an analog lowpass filter supplied with the output analog signal of the digital-to-analog converter, for eliminating frequency components substantially equal to or higher than 1/2 a sampling frequency F.sub.s of the discrete input digital signal of the signal processing circuit.
An intentional offset value is set beforehand. The intentional offset value is larger than a sensing objective signal "sig." A measuring device is provided for measuring the intentional offset value to obtain a measured intentional offset value "a" representing the quantity of the intentional offset value, and also for measuring a sum of the sensing objective signal "sig" and the intentional offset value to obtain a measured signal value "b" representing a summation of the quantity of the sensing objective signal and the quantity of the intentional offset value. A ratio (b/a) of the measured signal value to the measured intentional offset value is obtained. The obtained ratio is used as noise reducing data for reducing the noise involved in a sensor output.
An offset correction circuit is disclosed in a digital-to-analog coder (10) comprising a delta coder (18) providing a serial bit string at a high frequency F in response to digital words supplied at a low frequency F, and an analog integrator (22) providing an analog output signal (24) which is an analog representation of the digital words. The offset correction circuit avoids introducing an offset in the analog output of the integrator (22) when a PLO correction is taken to slow down or to speed up the clock controlling the input of the digital words. Such a circuit is implemented by a state generator which provides a corrected pulse in place of the sigma-delta data which lasts half the duration of the offset.
A D/A converter system for converting digital signal to analog signal includes a circuit for converting digital signal such as PCM signal to pulse density modulation signal, and an analog low-pass filter for converting the pulse density modulation signal to analog signal by removing noise from the pulse density modulation signal.
A digital to analog converter is employed in the digital line circuit of a telephone system and operates to convert a digital signal indicative of an analog speech signal back into a replica of the analog signal. The converter operates with an interpolated input digital signal to detect by means of a sign bit, the characteristic of an input digital word as being indicative of a positive or negative level. An error correcting signal is provided by the converter which is added to the next digital word to provide a compensated word having a sign bit determined by the remainder and the sign bit of the previous digital word. This word is then processed in sequence to produce an output pulse stream from the sign detector indicative of successive positive or negative values as defined by the input digital words, each of which are modified according to the error correcting signal.
