A protocol system for data processing equipment, particularly equipment used in building automation monitoring and control systems for air-conditioning control and monitoring of fire and security points is disclosed having a plurality of stations connected to a data bus, each station having an apparatus for monitoring the traffic on the data bus, calculating its turn to transmit or time slot during which it is permitted to transmit data on the bus and updating its calculated turn or time slot after each station designated to transmit in a turn or time slot after each station designated to transmit in a turn before it has transmitted data. Although each station has a designated time slot during which it may transmit, each time slot is of variable duration depending upon the extent of data to be transmitted. Thus, each station must be capable of calculating its time slot after each previous station has either transmitted or failed to transmit, and this station must calculate its own time slot accurately even though each previous station has transmitted for a variable length of time.
An architecture for a low-end, high-performance switch subsystem allows the connection of a multitude of requests per link. The switch subsystem operates a cross-bar switch under the control of a controller, such as a personal computer, to connect selected ones of a plurality of input links to selected ones of a plurality of output links. A data structure for the switch subsystem is mapped to the memory of the controller. The switch subsystem comprises three switch servers, a request server, a connect server, and an acknowledge server, which perform in a pipelined fashion. An interface protocol for the switching subsystem may be adapted to various applications and allows a connect request to be either queued in the switch subsystem until the requested output link in available or the requestor is notified immediately if the requested output link is not available, so that alternate actions can be taken.
A network of at least two modules M1, M2 which are addressable and connected by a standard transmission line, for example an electric power distribution network RDE. The modules are connected either to sensors CAPT or actuators ACTI, or to a processor TERMI. An order number is assigned to the modules. The transmissions from the modules are sequenced by measuring the time elapsed between the messages. The messages are active signals having a predetermined duration, and all signals of shorter duration are suppressed. The impedance of the modules is low during emission and otherwise. Applications to the fields of personal computers and of domestic electric power distribution.
Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. A plurality of status flip-flops is provided in each port for generating port parameter bits. The generated parameter bits are applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to ignore any parameter bits on the bus as long as the mask signal remains. This returns control of the port preference to any unmasked parameter bits and to the assigned port priority codes.
A multiprocessor system having a memory-programmable control of the type having a processor unit, coupling memories and input and output modules for transferring signals to and from a process which is to be controlled. Each processor unit is provided with a subprogram and a data memory which can be accessed directly, and a bus control unit releases access to the common system bus always for only one of the processor units. The access sequence and the access duration of the individual processor units to the common bus, via which the signals run to and from the controlled process, are fixed in a bus assignment matrix. In this manner, simple synchronization of the processor units is achieved. Moreover, guaranteed reaction times with respect to the process are possible. In addition to the duration, sequence, and frequency of the bus access of each processor unit in a bus cycle, the latest number bus window which must be seized by each processor unit can also be monitored by a bus monitoring device, thus insuring that guaranteed reaction times are possible.
System and method for controlling the transfer of data between a plurality of processors in a network. Synchronization between the processors is effected by means of asynchronously operated address counters which control the transmission of data from the processors. When a transmission occurs, the address counters are all set to a count corresponding to the address of the transmitting station, and in the event of a transmission from more than one processor, the address counters are reset to an initializing level. A station is permitted to transmit only when the count in its address counter corresponds to the address of the station.
