A plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low-speed memories are provided. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.
In a method of starting rotation of a magnetic disk medium of a large-capacity flexible disk by a spindle motor for use in a high-density type flexible disk drive for carrying out data recording and reproducing operation to and from the magnetic disk medium of the large-capacity flexible disk which requires to rotate at a high rotation speed on recording and reproducing, the method includes: a first step of rotating the spindle motor at a low rotation speed lower than the high rotation speed on rotation starting of the magnetic disk medium; a second step of rotating the spindle motor at the high rotation speed subsequently to rotating of the spindle motor at the low rotation speed; a third step of rotating the spindle motor at the low rotation speed subsequently to rotating of the spindle motor at the high rotation speed; and a fourth step of rotating the spindle motor at the high rotation speed subsequently to rotating of the spindle motor at the low rotation speed at the third step. The second and the fourth steps are carried out to ensure that the spindle motor chucks a disk hub of the large-capacity flexible disk. Each of the second and the fourth steps includes the steps of increasing the rotation speed of the spindle motor from the low rotation speed up to the high rotation speed by a predetermined abrupt acceleration; and rotating the spindle motor at a constant speed equal to the high rotation speed.
An impact of a memory latency time on repeat operations with a memory is reduced by providing a repeat start buffer for buffering a beginning of a data sequence to be repeatedly accessed, and a repeat switching unit, connected with the memory and the repeat start buffer, for switching therebetween for accessing the buffered beginning of the data sequence to be repeatedly accessed when the data sequence is to be repeated. In case of jump operations, a further reduction is achieved by providing a first and a second data buffer connectable with the memory for buffering data sequences, and a switching unit, connected with the data buffers for switching therebetween. The memory is accessible for each data buffer during an idle memory accessing time of the other data buffer for buffering a beginning of a data sequence to be accessed successively.
A packet data generator for generating complementary packet data which are added to information data for packet transmission via a high speed PCM transmission line. The packet data generator includes first and second memories for storing the complementary packet data; an address counter for counting an address at the timing of a synchronization signal of the high speed PCM transmission line; a multiplexer for changing the connection of the first and second memories; and a synchronization circuit for outputting a switching signal to the multiplexer in synchro with an output from the address counter. Since two memories are provided, while one memory is used for supplying complementary packet data at the data transmission speed, the other memory can be used for storing new complementary packet data at the CPU processing speed. The new complementary packet data are supplied by switching from the one memory to the other memory in synchro with a synchronization signal of the high speed PCM transmission line.
A data accelerator for use in a test vector sequencer includes a data translator, a plurality of sequence memory devices, and a switch. The data translator and the switch are configured via a control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to transfer a previously stored data segment. The test sequencer forwards a first application segment to a first memory device and acquires a subsequent application with a second memory device, detects a condition responsive to the completion of the segment acquisition and forwarding tasks, switches the roles of the first and second memory devices, and repeatedly switches and detects until all application segments have been processed.
A camera image data processor provides scan conversion at extremely high speed while allowing static and dynamic correction of image data particularly for a high data output rate CCD image transducer in a confocal imaging system for automated optical inspection in manufacturing processes. Scan conversion and data collation is accomplished at bit rates in excess of 1 Gigabyte by accessing a double buffer memory with different sequences of addresses covering a field of an image corresponding to a field in the memory during read and write operations. Highly parallel output is provided for confocal height data in a raster line by providing a delay equal to an integral multiple of the access time for a field for each confocally imaged height within a sample.
