In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment. INTRODUCTION CROSS REFERENCES TO RELATED APPLICATIONS U.S. Patent application of J. D. Dixon, one of the co-inventors herein, Ser. Nos. 866,425, filed Jan. 3, 1978 and 918,223, filed of even date herewith, both assigned to the assignee of the present invention, show and describe, but do not claim, portions of the invention claimed in the present invention. BACKGROUND OF THE INVENTION This invention relates to mechanisms for permitting program instructions and data to reside in the same or different pages of storage independently of each other and for facilitating communication between programs, or program segments, in different pages within a data processing system. More particularly, it relates to such a mechanism that is particularly useful in a small microprogrammed controller with insufficient address fields to access all of the storage which it is desired to utilize. An example of this type of small controller is shown and described at pages 3270-3273 of the Technical Disclosure Bulletin, Vol. 19 No. 9, published February, 1977 by the International Business Machines Corporation. The present invention is particularly useful in a microprocessor (or microcontroller) specifically adapted for control of I/O (input-output) devices. In such a controller maximum speed of operation, minimum cycle time is desirable. To optimize cycle time, all instructions are fixed at one processor cycle time--multiple fetches are not permitted. No address calculation is permitted. With these restrictions, paging is required to access memory larger than that defined by the maximum address structure in an instruction. Hardware paging is required for efficient instruction branches from one page to another. Paging mechanisms are known in the art and are often incorporated in processors where the maximum number of bits in the processor's address structure is insufficient to directly address all of the storage which is required for a particular application. Examples of paging structures are shown and described in the Technical Disclosure Bulletin, Volume 19 No. 8, pages 2877, 2878, and Volume 19, No. 9, pages 3266, 3267, published Jan. 1977 and February 1977 respectively, by International Business Machines Corporation. However, to the best of applicant's knowledge, no paging mechanism has been suggested which uses separate page registers, dynamically changeable under program control, for a program's instructions and its data so that the data may reside in the same page as, or a different page, than the instructions, independent of the instructions. With a minimum of hardware and software support, significant paging flexibility is achieved. In the preferred embodiment, the invention is incorporated in a micro-controller in which the instruction fetch and execute functions are overlapped. During the execution of one instruction, the next instruction is being fetched from memory. Care must be taken therefore in Branch and Link Type instructions to assure storing of the correct D/I bits with the current program instruction address bits. In a data processing system, particularly that part of a system which is used as a controller for, for example, a plurality of input/output (I/O) devices, it may be necessary for the system to execute separate control programs substantially concurrently even though they may run at asynchronous rates. In order to accomplish this, there must be a mechanism for transferring control between the two programs. A well known mechanism for accomplishing interaction between programs depends upon a hardware register which preserves, for a limited time, an indication of the memory address of an instruction in a program from which control was transferred. That instruction would typically be a (conditional or unconditional) branch instruction. If there would be a need to return control back to the original program, the contents of this register would have to be saved for subsequent utilization in returning. The saving of the contents of this register used storage (for the save instruction) and time (for the execution of the instruction) while accomplishing no other useful work. Some of the disadvantages of the system described above were overcome in the 1960's by the provision of a computer instruction called "Branch And Link". This instruction was implemented by hardware which, in response to the instruction, caused a branch to a particular address specified by the instruction, and automatically stored in a "link register" an indication of the address from which control was transferred. Subsequently, the execution of another instruction called "Return" would cause control to be transferred to the instruction at the address indicated by the link register. Thus, a programmer was able very easily to cause the exiting from a main stream of coding to a sub-routine, and then return to the main stream, by using two simple instructions with no need to concern himself with storing the contents of any particular registers. The improved paging structure of the present application must interact efficiently during these Branch and Link and Return instructions. SUMMARY OF THE INVENTION In the preferred embodiment, a novel paging mechanism is provided for efficient, yet flexible processor operation. A first hardware register I is provided to store the number (address) of the page in which the next instruction of the current program is stored and a second hardware register D stores the number of the page in which the next selected data for that program resides. By the use of Set Data Page (Set D) and Set Instruction Page (SI) instructions, the page numbers in the D/I registers can be changed at will by the programmer to achieve maximum flexibility in locating instructions and data. During instruction fetches, the I register contents are gated to a page decode circuit for selecting the page in which the instruction resides. At the same time, the offset address within the page is gated to a storage address register SAR to select the instruction location within the selected page. During data load and store operations the D register contents are gated to the page decode circuit to select the page in which the data resides; and the offset address within the page is gated to the SAR to fetch or store the desired data. The controller of the preferred embodiment has an overlapped instruction fetch/execution mode of operation. The formation of the address of the next instruction must therefore occur in the early part of the processor cycle. If, during a Set Instruction Page (SI) Instruction, the I register were set to the new page value and then the value were gated to the select circuit concurrent with setting the next address offset bits in the SAR, the SI instruction would in effect cause a branch to the new page; and, because the only offset address bits available are those in the SAR, the branched to address could only be that one offset address in the new page. This results in serious inflexibility. Hence, in the preferred form of the invention, the setting of the I register is delayed until the next instruction fetch is made, which fetch uses the old I bit. This causes fetching of the next sequential instruction after the SI instruction. This next instruction is one of the various Branch type instructions and includes within its branch address field the offset address of the branched to instruction in the new page defined by the new bit in the I register. A Set Data Page Instruction similarly sets the D register late in the execution cycle so that the old page value can be saved in the Link Register if a Branch and Link Instruction follows the Set Data Page Instruction. Another problem arises for the Branch and Link instructions which set the Link Register from the IAR register. For example, during a Branch and Link (BAL) Instruction which follows a SI instruction, the old D/I bits (prior to setting a new I bit in the I register) must be stored in the Link Register during the execution of the BAL instruction. However, during the preceding SI execution the old I bit was destroyed. Hence, in the preferred embodiment of the invention, a Delay register is interposed between the D/I registers and the Link Register. During each instruction execution, the contents of the D/I registers are gated into the Delay register. Upon occurrence of a branch and link instruction, the contents of the Delay Register will contain the old value of the D/I registers. As a result, the old D/I page values are available for storing in the link register whenever a new page value has been set (Set I or Set D) in the instruction cycle immediately preceding a Branch and Link type of instruction.
In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2.sup.n addresses such that there is paged and unpaged ROM and pages and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory. The method of using the paging apparatus includes creating a table in the unpaged RAM of all routines in the paged memory blocks and using the table to transfer from one routine to another. Within the table is a code identifying the page in which the new routine exists and an offset into that page used to determine the address in that page of the new routine.
A method and apparatus for monitoring the execution of a procedure having multiple exit points without modifying the software via breakpoints. The starting address of the procedure is loaded into an Instruction Address Break Register (IABR). Upon execution of the starting address the IABR raises an exception. The processing of the exception is used to implement a counting routine and for loading the IABR with the address of the calling party via the Link Register. Upon execution of the address of the calling party, the IABR once again raises an exception. The processing of the second exception is used for stopping the counter and performing any related analysis.
A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.
