A unity gain amplifier circuit is disclosed which is responsive to an input signal being applied thereto for sourcing current to an output terminal for driving a load. The unity gain amplifier comprises a differential amplifier having first and second differential inputs at which one input thereof the input signal is applied. A current mirroring circuit is provided for producing balance current drive to the differential amplifier and which is coupled to the output thereof. The output of the differential amplifier provides base drive current to a NPN transistor which is coupled in cascode configuration to a PNP transistor. In response to the input signal being applied to the input of the differential amplifier current is sourced from the collector electrode of the PNP transistor for providing both sourcing current at the output of the unity gain amplifier and for establishing feedback to the second input of the differential amplifier such that unity gain is established.
A differential amplifier (24, 26, 10 and 12) having a feedback network (30, 34, 32, 36 and 38) for increasing common output without loss of gain. Also disclosed is a constant current source (60), and a level shifting network (48, 50, 52 and 54) for shifting the D.C. level of the output signal to a D.C. voltage substantially near that of second current source (44). An output stage (84, 86, 90, 92 and 94) provides low output impedance, low D.C. bias power consumption and high current drive capability.
A peak storage amplifier for storing successive peaks of a waveform for a sufficient period of time to insure accurate data transmittal is provided. A differential amplifier is responsive to the waveform and drives a PNP transistor that provides an output. A capacitor stores the peaks of the output waveform as long as a clamp signal is received by a current source that inhibits the current source from sinking the output to ground. Since the PNP transistor is continually reversed biased and the base-collector capacitance is small, the storage capacitor's discharge due to the amplifiers inherent turn-off characteristics is minimized. A compensation capacitor coupled to the differential amplifier prevents the collapse of a Wilson mirror serving as a load to the differential amplifier.
A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.
