A linear DC power supply provides high efficiency with substantially lower total capacitance than prior art linear DC power supplies. The power supply includes first and second input terminals, first and second output terminals, a center tap transformer, first and second capacitors, first and second charging circuits, and first and second discharging circuits. The center tap transformer has a primary connected to the first and second input terminals and has a secondary with first and second phase terminals and a center tap terminal which is connected to the second output terminal. The first charging circuit is connected to the secondary and the first capacitor to fully charge the first capacitor during a first portion of each cycle. Similarly, the second charging circuit is connected to the secondary for fully charging the second capacitor during a second portion of each cycle. The first discharging circuit connects the first capacitor to the first output terminal and permits the first capacitor to fully discharge during a third portion of each cycle. The second discharging circuit connects the second capacitor to the first output terminal and permits the second capacitor to fully discharge during a fourth portion of each cycle. The total capacitance of the power supply is significantly reduced by permitting the first and second capacitors to fully charge and discharge during each cycle. As a result, the differential voltage across the capacitors is much greater than in conventional linear power supplies, in which a DC voltage and a small ripple voltage are maintained across a filter capacitor.
A voltage discharge circuit discharges the voltage across a charge storage device, such as a capacitor, at an output of a power supply. The discharge circuit may be used, for example, in a contrast power supply for an LCD panel. The discharge circuit uses one or more switches to control the coupling between the output capacitor and a discharge element, such as a resistor. When the power supply is enabled, the discharge resistor is not coupled to the output capacitor, so that the discharge circuit does not significantly affect the operation of the power supply. When the power supply is disabled, the switches couple the discharge resistor to the output capacitor to discharge any accumulated voltage at a relatively fast rate. For a contrast power supply for an LCD display, a switching power supply is preferred.
A charging/discharging circuit is formed of transistors Q1, Q2; resistors R1-R4; and a capacitor C. The series resistors R1, R2 are connected between the power supply line +Vcc and the circuit ground. The series resistors R3, R4 are connected between the line +Vcc and the circuit ground. The collector of NPN transistor Q1 is connected to +Vcc, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. The collector of PNP transistor Q1 is connected to the circuit ground, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. Capacitor C is connected in parallel to R2. The charged voltage of C is used as a reference potential VR for another linear circuit. Suppose that R1=R2, R3=R4 and +Vcc=10 V. When +Vcc rises from 0 V to 10 V but VR does not reach to 5 V, Q1 is forwardly biased so that C is quickly charged by the emitter current of Q1. When +Vcc falls from 10 V to 0 V but VR does not reach 0 V, Q2 is forwardly biased so that C is quickly discharged by the emitter current of Q2. When VR=5 V (stationary state), Q1 and Q2 are both cut-off, so that only small currents flow through the series circuits of R1, R2 and R3, R4. The time constant of (R1.vertline..vertline.R2).C can be made large so that VR is free from ripples of +Vcc.
A power supply circuit for a flash lamp delivers energy to the lamp in increments rather than in the conventional single charging pulse. A dc voltage power supply is used which has a voltage output considerably higher than the normal lamp voltage. The power supply output is connected across at least two circuits which are adapted to charge to some small increment of the total lamp energy requirements and then to discharge the stored energy into the lamp. Each circuit which contains a low value capacitor is cyclically connected between the lamp and the dc supply so as to create a continuous series of incremental inputs to the lamp, the inputs terminating when the desired lamp energy output is achieved.
A circuit for rapidly raising the value of voltage at a circuit node to a predetermined precise level including first and second charging circuits, and circuitry including a timing circuit responsive to an enabling signal for connecting the one of the charging circuits to the circuit node for a first limited period and then connecting the other of the charging circuits to the circuit node thereafter.
In a high voltage DC generator, the primary winding of a flyback transformer is responsive to an input pulse for inducing a high-voltage potential in the secondary winding. A first pair of first and second diodes are connected in series from one of the secondary windings to a first output terminal. A second pair of first and second diodes are connected in series from the other terminal of the secondary winding to a second output terminal. Two capacitors are cross-coupled between the terminals of the secondary winding and the junctions of the diodes of each pair. The first diodes of each pair are turned on in response to the input pulse and the second diodes of each pair are turned on in response to the cessation of the pulse. A ringing reduction circuit comprises a resistive element, a capacitive element and a diode element, the diode and capacitive elements being arranged such that when the first or second diodes of both pairs are conductive the diode element turns on the charge the capacitive element, the resistive element being in circuit with the capacitive element to pass a current in response to the cessation of the pulse to dissipate ringing energy during the trace period.
