This describes a differential amplifier for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage and comprises two identical voltage networks coupled between differential voltage inputs and to common differential current outputs and a common bias circuit. The described transmission line circuit operates as a transmission line receiver circuit with a high degree of common-mode rejection that will work in a high input signal voltage environment and in which both true and complement outputs can be developed such that their signal responses are additive and their common-mode responses subtractive. The circuit thus converts the input voltage to an input current while isolating the sensing circuit from common-mode input voltages which may be in excess of the breakdown voltage of the individual components of the circuit and the power supplies powering up the sensing circuit.

A complete type integrator is disclosed which is designed such that the time-constant thereof can be controlled; wide input and output dynamic ranges can be achieved; operation with low power supply voltage is possible; and no offset voltage is generated. More specifically, the integrator comprises an amplifier circuit having a combination of a first and a second differential amplifier circuit (A1, A2) and connected to the input side of an integrator circuit; and an offset eliminating circuit connected to that portion of the amplifier circuit where the input signal (9) is applied. The offset eliminating circuit comprises a combination of a first, a second and a third current-mirror circuit (B1, B2, B3).

A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

An improved capacitive feedback circuit (20) comprises a feedback capacitor (23) having its output terminal connected to a high-impedance node (N). More particularly, the improved capacitive feedback circuit comprises a first branch (24) having a bias current source (25), an amplifying element (26), and a current sensor (27) connected in series, the amplifying element having a high-impedance control terminal (26c). The feedback capacitor (23) has its output terminal connected to said control terminal (26c). A current-to-voltage converting feedback loop (28) has a high-impedance output terminal (28c) connected to said feedback capacitor output terminal.

A balanced current amplifier mirrors either a fully differential or single ended input signal into common output circuits in a manner to generate a fully differential output signal without any d.c. bias. Input signal nodes are maintained at a desired voltage by circuit elements other than those of the current mirror circuits, thus freeing the current mirroring elements from having to be sized for this purpose. The sizes of the output transistors are adjustable in order to set the gain of the circuit. In addition to amplifier circuits, a full-wave rectifier, a comparator, and a filter, all operating with current signals, are described. A single circuit module may include all of these circuits with a user provided the capability to program the module to perform any one or more of these functions.