A processor element is provided with a data transfer control circuit that sends out an address count pulse (ACNT) onto a control bus. N data transfer channels each contain a data transfer buffer and a buffer control circuit. The buffer control circuit comprises an identification number register, an input/output control circuit, an address counter, and a comparison circuit. The address counter holds a channel address that is preset in such a way as to allow each channel to take the same channel address number, and increments such a channel address each time it receives the ACNT. If the identification number and the channel address coincide, the data transfer buffer in the same channel is selected. The number of interconnecting wires can be reduced and the transfer of data can be carried out at a high transfer rate, in a multiprocessor system whose linking network between each processor is formed by a series of data transfer channels.

An arrangement for communication between two CPUs which allows diagnosis of whether the cause of an interrupt in communication between the CPUs is due to a routine interrupt or a failure in the communication line. Timers generate overflow signals in the event that data from one or the other CPU is late in arriving. Lateness is determined by comparing the timer values to stored values in memory. Control units respond to the timers and switch the transmission level of the CPUs so that they pass a predetermined signal pattern between themselves, indicating that the interrupt is in effect but that communication lines are still open. When one of the CPUs fails to detect the confirmation signal, the CPU causes a communication failure to be indicated.

A communication protocol for direct communications between operating system kernels of a plurality of processors in a clustered-type, shared virtual memory, multi-processor data processing system is disclosed. Each processor unit includes a intermachine communications software system ("IMCS") which may-be used by a trusted kernel of the operating system of the processor to communicate with a service in another processor, either directly or through an intermediate processor. Communications are initiated when a user prepares a message in accordance with pre-programmed instructions from the IMCS in a standard format. Once the message is prepared, the user calls IMCS which selects a route for the transmission of the message over a serial communications link to the receiving processor using a "request to send immediate" serial link level protocol. The message is initially directed to a common buffer pool. IMCS calls special software to read the header of the message to determine the identity of the destined server and to determine if the buffer in the buffer pool assigned to the called service has available buffer space to accept the message. If not, IMCS directs the sending of a negative acknowledgment to the sending processor. If sufficient buffer space is available, IMCS directs the sending of an acknowledgment to the sending processor. Upon receipt of the acknowledgment by the sending processor, IMCS calls a notification routine to inform the user of the status of the transmitted message.

An apparatus for controlling the access of a plurality of microprocessors at a data line. The microprocessors are connected by interface components or blocks, logic switching circuits and bus drivers with two lines or conductors. An access request or demand of a processor initiates a signal change at the first line. This signal change causes the transformation of data which is specific to the processor into a delay or a priority signal, upon the occurrence of which there is accomplished a signal change of the second line. As a function thereof there appears at an input of the interface component a signal change which is indicative of the availability of the data line. Upon simultaneous occurrence of access requests or demands of a number of processors the signal change of the second line is brought about by that processor whose priority signal possesses the smallest delay. The signal change of the second line prevents the occurrence of the priority signals possessing the greater time-delays and which are correlated to the remaining processors. At these processors there thus cannot occur any signal change at the input of the related interface component or block and which indicates the availability of the data line.

A concurrent processing system utilizes a generalized linearly expandable data transfer bus architecture to tightly couple data processors, memory and I/O devices. The system is suitable for multiple instruction multiple data processing, and operates by transmitting and receiving complete transaction codes fully identifying the target device by specifying a process code. Data processing memories and I/O devices may be dynamically assigned to a process by specifying the process code thus providing great flexibility in utilization of system resources. Processors, memories and I/O devices are connected together by means of interfaces which are connected to a bidirectional bus. The complete data transaction preferably occurs during one clock period, although four additional clock periods are used to complete a bus transaction, namely, arbitration, match recognition, data validation and acknowledgement of receipt. All the interfaces examine each transaction on the bus 5 preferably simultaneously, and allow the transaction to pass to a device and or I/O, if control registers in the interfaces correspond to those of transaction. The five bus transactions are overlapped in time so that a data transfer may occur with each clock cycle resulting in a data pipeline system of very high data transfer rates.