Distributed multiprocessor communication system

What is claimed is:

1. A distributed multi-data processor system wherein a plurality of processor modules, each of which contains a data processor, are distributed along a communication link by way of which the transfer of information from one processor module to another processor module may take place, and wherein the receiving processor module will acknowledge receipt of the information characterized in that each processor module includes:

means for repetitively generating a plurality of time-slots each preassigned to one of said processor modules;

first means, responsive to a request from said data processor for the transmission of a message to another processor module, for recognizing its preassigned time-slot and transmitting a message character during its preassigned time-slot, said message character containing the address of said another processor module and a priority code defining the priority level of the message character;

second means, coupled to said first means, for monitoring said communication link for acknowledgement of receipt of said message character by said another module, and enabling said first means to continuously transmit said message character during each successive occurrence of said preassigned time-slot until said another module acknowledges receipt of said message character and

means responsive to receiving the priority code of the message character for altering the priority level of all subsequent message characters which will be accepted by said another module.

2. A distributed multi-data processor system according to claim 1, wherein each processor module further includes

third means for monitoring said communication link for message characters containing the address of said each processor module, and causing data included in a message character which contains the address of said each processor module to be stored in that processor module.

3. A distributed multi-data processor system according to claim 2, wherein said third means includes means for latching onto said address-containing message character and for acknowledging receipt of said address-containing message character, over said communication link, during said preassigned time-slot.

4. A distributed multi-data processor system according to claim 2, wherein said priority code is representative of one of high priority and low priority modes, the first character of each message containing a low priority mode indication and each subsequent character of each message containing a high priority mode indication, and wherein said third means includes said altering means for preventing the reception of a message character and storage of data in a message character having a low priority mode indication subsequent to the reception of the first character of a message until that message has been terminated.

5. In a distributed multiprocessor system wherein a plurality of processor modules are distributed along a communication link by way of which the transfer of information from one processor module to another may take place, a method of controlling the transmission and reception of information conveyed by way of said communication link between processor modules, comprising the steps of:

assigning prescribed address codes to each of the processor modules in said system;

generating said address codes in each of the processor modules during respective intervals of time;

for each respective processor module from which the transmission of information to another processor module is to take place, transmitting a message character over said communication link only during an interval of time when the generated address code corresponds to the address code assigned for said each respective processor module, said message character containing the address code of the processor module for whom the message character is intended and a priority code defining the priority level of the message character;

at said each respective processor module, monitoring said communication link for message characters and causing data included in a message character which contains the address of said each respective processor to be stored in that processor module and

altering the priority level of all subsequent message characters which will be accepted from the transmitting processor module upon receiving the first message character.

6. A method according to claim 5, further comprising the steps of:

acknowledging receipt of a message character to the transmitting processor module from the message character receiving processor module, and preventing each transmitting processor module from further transmitting said message character during a subsequent occurrence of its assigned time interval in response to said acknowledgement of receipt of said message character by said message character-receiving processor module.

7. A method according to claim 5, wherein said monitoring step includes the step of preventing message characters addressed thereto from transmitting modules, after the first character in a message transmitted from that transmitting module has been received and stored in the processor module, from being received until the message from said that transmitting module has been terminated.

8. A distributed multi-data processor system wherein a plurality of processor modules, each of which contains a data processing unit, are distributed along a communication link by way of which the transfer of information from one processor module to another processor module is effected, characterized in that each processor module includes:

transmission means, coupled to said communication link, for transmitting a message character including a priority mode indicator to another processor module in the system and,

receiver means, coupled to said communication link, for monitoring said communication link for messages transmitted thereover, and for accepting only a message addressed to that particular module,

means for storing a prescribed code unique to that module and defining the address of the module corresponding to a time interval during which said transmission means may be enabled to transmit a message character to another processor module,

means, coupled to said storing means and to said transmission means, for repetitively generating a code sequence containing each of the prescribed codes which define the addresses of the respective processor modules of the system,

comparison means, coupled to said code sequence generating means and said storing means, for enabling said transmission means to transmit a message character upon the output of said code sequence generating means corresponding to the code stored in said storing means, and

means responsive to the transmission of said priority mode indicator for limiting the transmission of additional message characters to the one processor upon the subsequent generation of the code sequence defining the address of the one processor.

9. A distributed multi-data processor system wherein a plurality of data processor modules, each of which contains a data processing unit, are distributed along a communication link by way of which the transfer of information from one processor module to another processor module is effected, characterized in that each of said processor modules includes a communications interface unit coupled to said communication link and the data processing unit of that module and which carries out the transmission and reception of messages assigned a predetermined priority level between the data processor of that processor module and another processor module, and wherein each of said interface units include;

means for repetitively generating in the same time-frame a plurality of time-slots preassigned to and defining the address of each of said data processor modules,

means for recognizing the repetitive occurrence of the time slot preassigned to that processor module;

means for enabling each communication interface unit, in response to a transmission control signal from its associated data processing unit to transmit a message including a priority code component defining the priority level of the message over said communication link during the occurrence of its preassigned time-slot;

means responsive to the generation of the transmission control signal for causing that interface unit of the data processor module to which said message is addressed to receive and store said message in the addressed data processor module;

and means responsive to receiving said priority code component for changing the priority level of the messages to be stored in the data processor module.

10. A distributed multi-data processor system according to claim 9, wherein said enabling means includes respective transmitter means, contained in each communications interface unit, for transmitting, as a component of the transmitted communication, an address code corresponding to the address and preassigned transmission time-slot of the data processor module for which the communication is intended.

11. A distributed multi-data processor system according to claim 10, wherein said enabling means comprises respective storage means, contained in each communications interface unit, for storing an address code corresponding to the address and preassigned transmission time-slot of that data processor module, and respective comparator means, contained in each communications interface unit and coupled to said storage means and to said communications link, for comparing the address code component of a communication transmitted over said communication link with the address code stored in said storing means, and causing data included in the transmitted communication to be stored in the data processor module upon said address code component corresponding to the stored address code.

12. A distributed multi-data processor system according to claim 10, wherein said enabling means comprises, in each communications interface unit,

code generator means for repetitively generating a sequence of address codes corresponding to the respective address and preassigned transmission time-slot of each data processor module within said plurality of data processor modules,

storage means for storing an address code corresponding to the address and preassigned transmission time-slot of that data processor module,

comparison means, coupled to said code generator means and said storage means, for comparing the address codes in the repetitively generated sequence of address codes from said code generator means with the contents of said storage means and generating a transmission enabling signal upon an address code generated by said code generator means corresponding to the contents of said storage means, and

means, responsive to the transmission enabling signal generated by said comparison means, for causing said transmitter means to output the communication onto said communication link.

13. A distributed multi-data processor system according to claim 12, wherein said causing means further comprises, in each communications interface unit,

comparator means, coupled to said storage means and to said communications link, for comparing the address code component of a communication transmitted over said communication link with the contents of said storage means, and causing data contained in the transmitted communication to be received and stored in that data processor module upon said address code component corresponding to the stored address code.

14. A distributed multi-data processor system according to claim 13, wherein said causing means includes

means for storing the priority code component indicating the priority mode of communications which may be accepted by that data processor module, and

means, coupled to said comparator means and said priority mode indication storing means, for inhibiting said comparator means from causing data contained in a transmitted communication to be stored in the data processor module unless the priority mode represented by the priority code component of the transmitted communication corresponds to the stored priority mode indication.

15. A distributed multi-data processor system according to claim 13, wherein each interface unit further comprises means, coupled to said comparator means, for transmitting a message receipt acknowledgement signal over said communication link in response to said comparator means causing a communication transmitted from another data processor module to be received and data contained therein stored, to thereby inform said another data processor module that the transmitted communication has been received.

16. A distributed multi-data processor system according to claim 15, wherein said causing means includes

means for storing said priority code component indicating the priority mode of communications which may be accepted by that data processor module, and

means, coupled to said comparator means and said priority mode indication storing means, for inhibiting said comparator means from causing a transmitted communication to be received and data contained therein stored in the data processor module unless the priority mode represented by the priority code component of the transmitted communication corresponds to the stored priority mode indication.

17. A distributed multi-data processor system according to claim 15, wherein each interface unit further comprises means for selectively coupling an interrupt signal to the data processing unit to which the interface unit is coupled in response to said comparator means causing data contained in a communication transmitted from another data processor module to be stored.

18. A distributed multi-data processor system according to claim 17, wherein each interface unit further comprises means, responsive to the transmission of a communication by that interface unit to a receiving data processor module and responsive to receipt of a message receipt acknowledgement signal from said receiving data processor module, for selectively coupling an interrupt signal to the data processing unit to which said that communication interface unit is coupled.

19. A distributed multi-data processor system according to claim 18, wherein said enabling means comprises means for synchronizing the code generator means in each of the communications interface units of the data processor modules of the system.

20. A distributed multi-data processor system according to claim 19, wherein said communications link comprises an intermodule communications bus connected exclusively to each interface unit, said bus containing address, data, and control lines, and wherein each communication transmitted from one interface unit to another is comprised of a data component coupled over said data lines, said address code component coupled over said address lines, and a control component including said priority code and a signal for synchronizing said code generator means coupled over said control lines.

21. A distributed multi-data processor system, according to claim 20, wherein said control lines include a line over which said message receipt acknowledgement signal is transmitted from a communication receiving interface unit to a communication transmitting interface unit.

22. A distributed multi-data processor system, according to claim 20, wherein each interface unit includes means for transmitting a complete message as a sequence of discrete communications, the priority mode of the first communication of the message being of a low priority and the priority mode of the second and subsequent communications of the message being of high priority, and wherein each interface unit includes means for causing said priority mode indication storing means to store an indication of low priority mode until the first communication of a message is received and data contained therein is stored and for causing said priority mode indication storing means to thereafter store an indication of high priority through the completion of the message.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates to a distributed multi-data processor communication system, and is particularly directed to a scheme for carrying out communications between processor modules distributed along a commonly shared communications bus without the necessity of continuous monitoring of the system communication channel by individual processors to which messages may be addressed.

BACKGROUND OF THE INVENTION

With the development and expansion of computer terminal equipment, such as that employed in electronic point-of-sales terminals, the demand for terminals which are capable of performing a plurality of specialized tasks has resulted in the creation of equipment which contains a plurality of microprocessors, each of which may be tailored to perform one specific task within the overall system. Concomitant to this multi-processor configuration is the need for a communication scheme which affords rapid, real-time communications between the independent processors. In conventional systems, each processor, in addition to performing one dedicated function, has been burdened with the task of looking for intermodule communications to which it must respond.

Typically, data is placed on a common intermodule bus to which each processor module in the system is coupled. This data contains the address of a target module for whom the particular message is intended and all CPUs within the system decode the address portion of the message in order to ascertain for whom the data is intended. This means that all CPUs must continually look at the intermodule bus and decode data; yet, only that module for which the data is intended will respond. This conventional approach is time consuming, the microprocessor being inherently too slow to perform this task efficiently, and usually a great deal of software is required in order to distinguish between addresses or commands, and each CPU may be unnecessarily burdened.

Now, various attempts have been proposed to relieve the central processor of these communication channel monitoring duties. For example, the U.S. Pat. No. to Beausoleil et al. 3,400,372 describes a multi-data processing system wherein the interfacing of two processors is effected through a processor-to-processor adapter, which becomes coupled to each computer when an interprocessor communication is to proceed. This technique may be termed a quasi-third party control scheme since each processor communicates by way of the third party (the channel adapter) under CPU control. The system is limited in that it is strictly limited to interfacing two processors, the communication itself is dependent upon interrupt acknowledgement before proceeding and, once begun, both the transmitting processor and the receiving processor must suspend all other tasks until the message is complete.

The use of a third party interfacing scheme is also disclosed in the U.S. Pat. No. to Broderick et al. 3,483,520 which describes a "mail-box" technique of routing multi-processor communications. All communications are routed through a central control sub-system (CCS) which contains all the interfaces for the processors that form part of a "star" configured network. All communications depend on one element, the CCS, so that if it fails, all communications cease. Such an approach has obvious shortcomings.

The case of a common bus scheme to perform data transfers among individual modules units is described in the U.S. Pat. No. to Bergh et al. 3,820,079 which discloses a multiprocessing computer wherein communications within one computer are conducted by way of module control units, each of which communicates with other module control units. The modules themselves are not independent processors, however, and because of a priority scheme through which use of the bus is defined, intermodule communications are not guaranteed, but are subject to bus availability. This problem of bus-lockout also exists in the bus communication system described in the U.S. Pat. No. to Schlaeppi 3,480,914 which describes a scheme wherein individual bus adapters are employed for each processor. Each adapter or interaction control unit responds to commands appearing on the common bus transmitted from other adapters to permit seizure of the bus. It is not until an interaction control unit has completed its use of the bus that control of the bus may pass to another adapter.

A further system in which a common bus is used for multi-module coupling is described in the U.S. Pat. No. to Trantanella 3,470,542. However, rather than relate to communications between independent processors, this system is directed to the transmission of signals between module units such as keyboards, printers memory, etc.; at any given time, one of the modules assumes control of the entire system.

Thus, although various prior art systems include techniques developed to control communications between various units in a digital data handling system over a common communication channel, such systems have not provided an efficient scheme for guaranteeing communications between multiple processors over a common communication link, while also relieving the individual processors of having to continuously monitor the channel for communications, thereby impeding intended data processing functions.

SUMMARY OF THE INVENTION

In accordance with the present invention, in a distributed multiprocessor communication system the CPU is relieved of the burden of bus management by a scheme which multiplexes the interprocessor module communications bus, to which all processors are guaranteed access, so that only an addressed CPU is allowed to be interrupted from performing its dedicated data processing function. Associated with each independent processor is a communications interface unit or communications network routing unit which relieves the processor of the task of decoding communications on the interprocessor or intermodule communications bus and, in addition, upon decoding its address and buffering message data, generates a handshake over the bus back to the sender during a designated time slot, thereby informing the sender that the transmitted message was actually received. Moreover, if one module is in a high priority mode of communication with another module, all lower priority messages are prevented from entering that particular module; yet, any other pairs of modules may still communicate. In other words, no module can possible tie up the bus, preventing other modules from communicating.

Transmission, reception, priority discrimination, and handshake are completely independent of CPU operation once the data is placed on the bus system, so that the time required to transfer a data byte is independent of any processor in the system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a distributed multiprocessor system having an interprocessor communications bus;

FIG. 2 is a block diagram of components of which an individual processor module in the distributed multiprocessor system shown in FIG. 1 may be comprised;

FIG. 3, comprising FIGS. 3A and 3B, is a schematic diagram of the transmitter portion of a communications network routing (CNR) unit contained within an individual processor module; and

FIG. 4, comprising FIGS. 4A and 4B, is a schematic diagram of the receiver portion of a communications network routing (CNR) unit contained within an individual processor module.

DETAILED DESCRIPTION

A distributed multiprocessor network is illustrated in FIG. 1 and may be comprised of an N number of independent processor modules 11-1 to 11-N, each of which modules is assigned the task of performing some specified function, through the use of its central processing unit (CPU), and which may be called upon by another module or itself may request another module to perform its own specified function in the course of system operation. The processor modules are distributed along an interprocessor bus 10 and communicate with one another through this commonly shared bus 10. In addition to a central processing unit, memory, and input/output (I/O) unit, each processor module may contain further functional processing units, such as keyboard control units coupled to a peripheral keyboard/display. Moreover, the I/O unit of each module may be coupled to a prescribed peripheral device, such as a printer or tapedeck, for example. Each individual processor module 11-1 to 11-N may be configured to be different from the rest so that the overall system may be tailored by a combination of those processor modules whose functions meet the criteria demanded by the user. Thus, a system may contain as few as one processor module, but usually contains a plurality of such modules whose total functional performance meets a multitude of user needs.

In order for a multiprocessor system to perform each of its intended functions, information must by capable of being transmitted to and from the various processor modules which make up the system, so that each module may cooperate with the other processor modules of the overall system and enable the system to perform all transactions for which it has been designed. Since the transmission of data, in and of itself, between processor modules, involves time not devoted to information processing, a reduction in the time required to effect communications between modules and relieving the processor module CPU of the task of overseeing and monitoring data transmission and reception are sought-after performance features for efficient system operation. These performance features are achieved in accordance with the present invention by incorporating into each processor module a further functional unit, hereinafter referred to as a communication network routing (CNR) unit, which relieves the CPU of the task of monitoring communications between separate processor modules and which operates so as to guarantee each processor module the same opportunity to use the interprocessor bus.

A block diagram of a typical processor module 11-1 to 11-N and the incorporation of a CNR into each processor module is illustrated in FIG. 2. As is shown therein, a CPU 21, I/O unit 22, memory 23, and CNR 24 are coupled to an intraprocessor bus 25 by way of which data, address, and control information are transmitted within the module itself. Intraprocessor bus 25 and the connections to it may be of a conventional configuration and, as such, do not form the subject matter of the present invention. Rather, the scheme by way of which a processor module communicates with another processor module is the subject matter to which the invention is directed and, accordingly, the following description will be directed to the details of the CNR and its operation in effecting transmissions between processor modules 11-1 to 11-N over intermodule bus 10.

The CNR 24 within each processor module responds to requests from its associated CPU 21 for communication with another processor module and also monitors the intermodule bus 10 for transmissions from other modules. For this purpose, each CNR contains transmitter, receiver, and associated control logic circuitry. In order to facilitate an understanding of the responsibilities of each CNR, the transmitter and receiver portions of a CNR will be separately described, followed by an explanation of system operation for an exemplary intermodule communication carried out by the CNRs of the transmitting and receiving processor modules, respectively.

CNR TRANSMITTER CONFIGURATION

Referring now to FIG. 3, there are shown the circuitry components of the transmitter portion of a CNR 24 and the bus connections for both intramodule and intermodule communications. The CNR control circuitry which is common to both the transmitter and receiver portions of the CNR is illustrated in each of FIGS. 3 and 4 in order to facilitate a complete description of each of the transmitter and receiver operations, and duplication of the control circuitry components in FIGS. 3 and 4 is accompanied by the same reference numeral designations.

The interprocessor bus 25, by way of which communications within the processor module itself are carried out, is coupled via four separate ports 49 through 52, respectively designated as PORTs A, B, L, and K. PORT A 49 is a bidirectional data bus port which couples the data-conveying portion of bus 25 via lead 83 to data register 48 for buffering data prior to transmission. In the exemplary illustration shown, data register 48 is an eight-bit storage register, the contents of which are coupled via drivers 59-66 over lines 93-100, respectively, to the data-conveying portion of intermodule bus 10. Of course, the number of data bits is not limited to eight, but may be expanded or reduced to meet system design. The data itself, which is coupled to PORT A via intraprocessor bus 25, may be stored in memory 23 (FIG. 2) prior to transmission and read out a character at a time to be temporarily retained in register 48 for transmission. PORT B 50 is a bidirectional control bus port for controlling the priority and destination of data from one processor module's CNR to another processor module's CNR. Lead 82 represents a four wire path from PORT B to priority/I.D. (identification) register 47. Three of the wires carry a three bit binary code designating the address of the CNR for whom the transmission is intended, while the fourth bit is a priority bit representative of the mode of operation of the CNR. The contents of register 47 are coupled to intermodule bus 10 via drivers 55-58 and output bus leads 89-92.

PORT L 51 is a pulsed CNR control port which couples control signals from the CPU to various logic elements of the transmitter circuitry necessary for operation of the CNR. PORT K 52 is a latched data CNR control port for programming the identity of the processor module relative to the other modules in the system as assigned during initialization of the system. A three bit binary code generated at initialization is supplied over line 73 to CNR I.D. register 37. A further output of PORT K 52 is coupled via line 71 to driver 33 which is coupled to the carry output of a three bit binary counter 32 of the control logic portion of the CNR. The carry output of the counter 32 of one of the CNR units in a system is employed to control clock synchronization of all the other CNRs which are coupled to the intermodule bus 10; the occurrence of this "bus sync" signal is indicated to each processor of the system via a designated bit of PORT K which is coupled to driver 33 and inverter 34 via line 71. The output of inverter 34 controls driver 35, the output of which driver controls the resetting of divider 31 and counter 32. The processor module chosen as the bus sync control module has that bit of PORT K to which line 73 is coupled set to cause the carrying output of counter 32 to be coupled via line 69 to the interprocessor bus 10 for use by every other CNR, while the corresponding bit of PORT K of the other processor modules is set to inhibit the coupling of their counter 32 carry outputs to the interprocessor bus 10, while enabling driver 35 to couple the carry signal from the bus sync control module's counter 32 to be applied via line 70 to the reset inputs of their respective divider and counter circuits 31 and 32.

As has been mentioned previously, one of the advantageous features of the present invention is that each processor module is guaranteed the same opportunity to transmit information to another processor module. To this end, the fundamental control of the transmission of information from a CNR is effected by the n-bit counter 32 (three bits in the exammple illustrated) which counts clock pulses at a prescribed rate and recycles at capacity to begin counting anew (as a carry signal is generated). The various binary codes established by the n-bits of the counter 32 correspond to the respective addresses of the processor modules 11-1 to 11-N of the system. Thus, for a three bit counter 32, there are a maximum of eight codes that can be assigned as addresses of processor modules between which communications may take place. It is, however, to be understood that the invention is not limited to a system having a processor module capacity of eight, but may be expanded or reduced as the case demands, simply by varying the count capacity and corresponding I.D. codes for the processor modules.

Referring again to FIG. 3, the n-bit counter 32 is depicted as a three-bit binary counter which counts clock pulses supplied over line 68 from the divider circuit 31. Divider circuit 31 divides the processor system clock frequency supplied over line 67 (which clock controls the overall processor operations at a relatively higher rate) by a suitable number to thereby sequentially step through the addresses (or time slots) assigned to the respective CNRs, which permits the completion of necessary intramodule operations for information transmission (or reception). In order that a particular CNR 24 will known when to transmit, a comparator 36 is coupled via lines 110-112 to the respective stages of counter 32 and via lines 113-115 to the respective stages of register 37. When the contents of counter 32 match the processor I.D. stored in register 37, comparator 36 supplies an output over line 84 to one input of AND gate 38. The other input of AND gate 38 is coupled via line 85 to the Q output of TRANSMIT "ON" flip-flop 39. TRANSMIT "ON" flip-flop 39 is employed to turn-on the transmitter. Namely, unless flip-flop 39 is in the set state, that CNR is incapable of sending data to another processor module. The set input of flip-flop 39 is coupled via line 75 to a control logic circuit 150, while its reset input is coupled to the output of an OR gate 40. Control logic circuit 150 is coupled to the intraprocessor system bus 25 and to the CPU 21 via RESET and SYNC lines 72 and 152, and generates various control signals in accordance with the system clock so that the operation of the transmitter, as well as the receiver portion of the CNR, may proceed in a prescribed sequence. In order to provide a concise illustration and description of the invention the details of the control logic circuit 150, per se, have not been shown, particularly since its implementation may consist of straightforward combinational logic, given the input and output signals described herein. Basically, control logic circuit 150 supplies a signal on line 74 to load the data applied to PORT A in register 37. It also supplies a signal over the line 75 to the set input of TRANSMIT "ON" flip-flop 39, to the load or write input of register 47, and to one input of an OR gate 43, the output of which gate 43 is coupled to the reset input of a TRANSMIT ACKNOWLEDGE flip-flop 42. TRANSMIT ACKNOWLEDGE flip-flop 42 serves the purpose of storing an indication of whether or not a transmitted character has been received or captured by the processor module for whom the message was intended.

The Q output of TRANSMIT "ON" flip-flop 39 is coupled over line 85 to one input of AND gate 38 so that, in response to an output over line 84 from module I.D. comparator 36, and with TRANSMIT "ON" flip-flop 39 having been set, AND gate 38 will supply an enable signal via line 86 to AND gate 53 and driver circuits 54-66. Driver 54 is hardwired to a "1" bit input and its output is coupled to the intermodule communication bus 10 via line 88, to indicate that the contents of the priority bit, the destination receiver I.D. bits, and the data bits of the intermodule communication bus 10 represent valid information. The second input to AND gate 53 is coupled to a "handshake" lead of the interprocessor bus 10 via line 87. If the processor module for whom the transmitted information is intended actually receives (or captures) the transmitted data, it will indicate receipt of the data via the handshake lead, thereby causing line 87 to go high and an output signal will be generated by AND gate 53 to set TRANSMIT ACKNOWLEDGE flip-flop 42, causing its Q output to go high and thereby inform the transmitting module of receiver data capture. The output of flip-flop 42 is coupled over line 81 to one-shot or delay circuit 41, one input of AND gate 46, and to one bit of PORT B 50. The output of delay 41 is coupled over line 101 to one input of OR gate 40. After a prescribed interval, subsequent to the receipt of a handshake signal, which sets TRANSMIT ACKNOWLEDGE flip-flop 42, one-shot 41 generates an output which is coupled via OR gate 40 to reset flip-flop 39. Flip-flop 39 is also reset via OR gate 40 by the processor reset signal coupled over line 72 from the CPU. This processor reset signal is further coupled via OR gate 44 to the reset input of TRANSMIT INTERRUPT ENABLE flip-flop