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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to automatic systems for horizontally
segmenting lines of text and then displaying the line segments. More
specifically, this invention relates to a proportional spacing system
which effects the display of line segments based upon the location of a
cursor and beginning with whole characters.
2. Description of the Prior Art
The scrolling of text up and down in a vertical direction on the face of a
display device has been known and used for some time. Also, the automatic
scrolling or segmenting of text and other information in the horizontal
direction is considered old. Considered new as far as this invention is
concerned is a horizontal segmenting display system which can be used for
efficiently handling text and other information made up of standard and
proportional width characters. As far as the display of text made up on
only standard width characters is concerned, no unsurmountable problems
have been encountered. This is because the characters and spaces adjacent
the left edge of a display segment will always be vertically aligned. When
text made up of proportional width characters is considered though, a
problem exists in generating partial characters to effect proper relative
placement in the vertical direction. Up to now, there has been no known
economical way to handle partial characters adjacent the left edge of the
display. This problem is solved with the system of this invention in that
partial characters are replaced with equivalent width spaces. The
resultant is a ragged left edge, but the characters are aligned vertically
as they would be printed. Also, the system of this invention is structured
such that both proportional and standard width characters can be readily
handled. With this being the case, a scale line made up of standard width
characters and symbols can be displayed along with text made up of
proportional width characters. Therefore, the display of a corresponding
segment of the scale line in standard width characters and symbols will
provide an operator with a page location reference means equivalent to a
standard typewriter scale.
SUMMARY OF THE INVENTION
A system is provided which effects the automatic segmentation of both text
lines and a scale line which are to be displayed. Segmentation is
dependent upon the location of a cursor in one of the lines of the text.
The system is structured to handle both standard and proportional width
characters. Each line, beginning with the line containing the cursor, is
sequentially loaded into a line buffer. Following the loading of the first
line, a segment including the cursor is selected. This segment is loaded
into a refresh buffer for display. Then the corresponding segment of each
following line, including the scale line, is selected and loaded into the
refresh buffer for display. Upon repositioning of the cursor beyond either
the left or right edge of the display, the above operation is repeated
beginning with the loading of the cursor line into the line buffer. The
occurrence of a partial character adjacent the left edge of a segment will
result in a space fill-in for display.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a pictorial representation of a partial page of stored text which
is to be displayed, edited, and printed on a sheet.
FIG. 2a is a pictorial representation of a display of a horizontal segment
of the text shown in FIG. 1.
FIG. 2b is a pictorial representation of a display of another horizontal
segment of the text shown in FIG. 1 partially overlapping the first
segment shown in FIG. 2a.
FIG. 2c is a pictorial representation of a display of yet another
horizontal segment of the text shown in FIG. 1 partially overlapping the
second segment shown in FIG. 2b.
FIG. 3 is a block diagram illustrating the overall system of this
invention.
FIG. 4 illustrates the structure included in the display control logic
block of FIG. 3.
FIG. 5 illustrates the structure included in the cursor logic block of FIG.
4.
FIG. 6 illustrates the structure included in the segmentation logic block
of FIG. 4.
FIG. 7 illustrates the structure included in the scale logic block of FIG.
4.
FIG. 8 illustrates the structure included in the line move logic block of
FIG. 4.
FIG. 9 illustrates the structure included in the tab logic block of FIG. 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Operations to be Performed
For a clearer understanding of the invention, the operations to be
performed will be discussed first. In referring to FIG. 1 there is shown a
partial page of text made up of vertically defined lines of information.
It is to be assumed that this page of text is stored in a text buffer.
Stored in the text buffer along with the alpha/numeric characters and
spaces shown are the cursor, the mode, the measure, and appropriate
control codes. The measure is the distance between left and right margins
for the text. The measure can be stored in terms of the locations of the
left and right margins relative to a zero writing line position. In this
preferred embodiment the left and right margins vertically define the text
information. The zero writing line position is the left most printing
position on a printer being used. The location of the cursor is the point
of operation for editing purposes. The cursor has been shown as the
highlighted and underlined "O" in the word OF in the first line. This is
for purposes of illustration only. In actuality it will only be a
high-lighted character created by a brightening bit in the character byte.
For example, if 8 bits make up the character byte, seven can be used for
the character itself and one for brightening in a well known manner. The
setting of the mode can be in terms of designating proportional spacing or
10 or 12 pitch standard spacing. When the term proportional spacing is
used hereinafter, it is meant to include escapement for proportional or
varying width characters, spaces, etc. The term standard spacing is meant
to include escapement for standard or equivalent width characters, spaced,
etc. The control codes utilized can be many including carrier return or
line end codes, tabs, etc.
Another assumption to be made is that the text illustrated in FIG. 1 is to
ultimately be printed out on a sheet following editing. If this text has a
measure width exceeding the width of the display device being utilized,
the display of the text for editing purposes must be in segments. That is,
the text must be horizontally scrolled.
For efficient utilization of the display device, the display of the first
segment will begin at the left edge of the display. Therefore, the left
margin space between the left edge of the sheet and the left margin will
not be displayed. This is illustrated in FIG. 2a wherein the first of
three display segments is shown. Yet another assumption here is that the
text is made up of proportionally spaced characters and spaces.
In determining which segment to display, the lowest order segment
containing the cursor is selected. Since the "O" in OF in FIG. 1 is the
cursor location and can be displayed in the first segment, this segment is
displayed as shown in FIG. 2a. The segment widths are different for
proportional and standard spacing, and are defined in escapement units.
This will be brought out in greater detail later in the specification.
Referring to FIGS. 2a, 2b, and 2c, each of the segments overlap to a
certain extent. This overlap provides an operator with a reference to text
in adjoining segments. Once a segment is selected though, operation
remains therein until the cursor is moved either to the right or left to a
position which is outside the segment. When the cursor is moved to the
left and outside of the second segment, automatic segmentation will occur
and the first segment will be displayed. If the cursor is moved to the
right and outside of the second segment, automatic segmentation will again
occur and the third segment will be displayed.
Referring next to FIG. 2b in conjunction with FIG. 1, if the cursor were
the "D" in DRAWING, it can be displayed in either the second or third
segment. In this case, the second segment is selected as shown in FIG. 2b.
If the cursor were the last "a" in the second line of FIG. 1, it can only
be displayed in the third segment as shown in FIG. 2c.
Referring again to FIGS. 2a, 2b, and 2c, a scale line including abbreviated
escapement numerals and dots, tab carrots, and a right margin rectangle
are displayed. The structure for, and technique of, creating this line
will be brought out more fully later in the specification. For now, it is
only important to note that the beginning of the display of the scale
corresponds to the left margin of the sheet to be printed. For example, if
FIG. 1 represents a printed sheet with a left margin (LM) twenty
escapement units to the right of the left edge, the displayed scale begins
with "2". This provides the operator with a visual indication of the
relative position of the displayed segment to the page or sheet to be
ultimately printed.
Referring specifically to FIG. 2c, a part of the character "H" is shown
dotted in adjacent the left edge. This will not be displayed. Instead,
there will be a space fill-in and the first character displayed on the
line will be the character "E" in the position shown. This will be brought
out in greater detail later in the specification.
Overall System
Referring next to FIG. 3 there is shown a block diagram generally
illustrating the overall system according to this invention. Specific
details of various of the system components will be set out with reference
is made to subsequent figures. Data including codes representative of the
text illustrated in FIG. 1 are first derived from, or generated by, data
input and formatter means 1. This means can be a keyboard, data
transmission line, etc. The data generated by data input and formatter
means 1 include character codes, space codes, control codes, mode and
measure codes, cursor codes, tab codes, etc. Each of these codes is
applied along line 3 and stored in text storage buffer 2. The storage
locations in buffer 2 are determined by address pointer 46. The control
codes from means 1 such as the cursor, end of text location, etc., are
also applied along line 5 and stored in text storage registers block 4.
Registers block 4 includes a decode, and addressing and gating means for
effecting the storage therein of these control codes. Text storage buffer
2 can be an electronic dynamic shift register, random access memory, etc.
Control codes denoting the left and right margin locations, and standard
and proportional (PSM) spacing modes are applied along line 7 and also
stored in output parameter registers block 6. Registers block 6 includes a
decode, and addressing and gating means for effecting the storing therein
of these control codes. The reasons for storing control codes in registers
blocks 4 and 6 in addition to buffer 2 is to assure their timely
availability when required by other portions of the system. The control
codes stored in output parameter registers block 6 are applied along line
9 to character generator 8 and along line 11 to display control logic 10.
The control codes stored in registers block 4 are applied along line 45 to
logic 10. Line beginning location codes are applied along line 12 to line
begin registers block 13 for storage therein. Registers block 13 includes
a decode, and addressing and gating means for effecting the storage
therein of the line beginning codes. The line beginning location codes are
applied along line 14 to display control logic 10. If data input and
formatter means 1 is a keyboard connected to a printer having an
escapement and tab rack, there is an associated address pointer 15 for
addressing the printer carrier location and the escapement and tab rack
(tab stop array) 16 during carrier escapement. Address pointer 15 is
utilized in effecting the storage of tabs.
When a number of lines are to be displayed from text codes stored in text
storage buffer 2, display control logic 10 addresses text storage buffer 2
along line 19. This is to locate the beginning of the line containing the
cursor. Codes making up the cursor line are then output from text storage
buffer 2 along line 20 to display control logic 10. As each code is read
into display control logic 10, there is an addressing of escapement ROS
(read only store) 21 along line 22. This is to determine, in the case of a
character for example, the escapement thereof dependent upon the spacing
mode input along line 11. The escapement for the character is output from
escapement ROS 21 along line 23 to display control logic 10. Each
character (and space) code making up the line is then applied along line
29 and written into the line or intermediate buffer 24 in a location
determined by address pointer 25. Only character (and space) codes are
stored in buffer 24.
The control of DMA (direct memory access device) 26 addresses buffer 24
along line 28. The control by the DMA 26 of the write-in and later
read-out of characters to and from intermediate buffer 24 is along line
30. Again, no control codes or character codes with cursor bits turned
"on" are stored in buffer 24 during accumulation of character codes for
text lines.
The control of DMA 26 for obtaining the appropriate segment of the scale
line to be displayed is along line 27 from display control logic 10. DMA
26 addresses scale image ROS 31 along line 33. The scale image or line
information made up of character and symbol codes is then applied along
line 32.
This information is then applied along line 30 and stored in buffer 24 in
locations addressed by pointer 28. Following the accumulation of codes for
each line, including the scale line, DMA 26 causes the codes to be applied
along line 35 and stored in refresh buffer 34 at locations determined by
address pointer 36.
Following the output of the cursor character code from text storage buffer
2 to display control logic 10, the refresh buffer cursor location is
applied along line 38 and stored in cursor register 37. This is to
identify the cursor character code when input to character generator 8
from refresh buffer 34. The result is a brightened character on the face
of CRT 44. Cursor register 37 is connected to character generator 8 by
line 40.
The address line 119 and the data line 123 are used for connecting the line
move logic portion of the display control logic 10 to refresh buffer 34.
This will be more fully appreciated when reference is made to FIGS. 4 and
8.
With the first line segment containing the cursor stored in refresh buffer
34, the corresponding segments of following lines to be displayed are
sequentially determined by display control logic 10. In turn, DMA 26
causes these segments to be loaded into refresh buffer 34. Following the
loading of all corresponding segments (of all lines to be displayed) into
refresh buffer 34, the corresponding segment of the scale line is
determined and loaded into refresh buffer 34. Other operations are
performed on the scale line and these will be brought out later in the
specification.
The segments of the lines to be displayed have now been formatted and
stored in refresh buffer 34. The character (and scale line symbol) codes
making up these segments are now output along line 39 to character
generator 8. The characters are generated and applied along line 41 to
video control 42. Then they are applied along line 43 to display device
44. Display device 44 can be a CRT (cathode ray tube), gas panel, etc.
Display Control Logic
Referring next to FIG. 4, there is shown the structure included in the
display control logic block 10 of FIG. 3. At the beginning of operation, a
current line number register 45 is set along line 46 to the cursor line
number. The output of register 45 is along line 47 to register multiplexer
48 which addresses line begin registers 13 (FIG. 3) along line 49 to
locate the beginning of the cursor line. The output along line 14 is to
current text position counter 50. This is used in addressing text storage
buffer 2 along line 19 to locate the cursor line. The output of the text
storage buffer 2 is the first data code (character, etc.) of the cursor
line and this code is applied along line 20 to current data register 51.
This code in turn is applied along line 52 to decode 53 for determining
whether it is an end of line code, tab code, backspace code, text
character or space. This code is also applied along line 22 to escapment
ROS 21. The escapement for the code, if a backspace or text character or
space, is then applied along line 23 to character escapement register 54.
The escapement is input to adder 55 along line 56. The output of adder 55
is to current total escapement register 57 along line 58. A backspace code
along line 22 will result in a subtract operation in adder 55. Register 57
stores the running count of escapement units from the left margin. This
operation continues for each character, space, and backspace code until
either a tab code or end of line code appears on line 20.
A point to note is that adder 55 is made up of sequential rather than
combinational logic. Thus, the output along line 58 is not updated until
clocked by an input along line 502 from AND gate 129. The inputs to AND
gate 129 are adder clock from clock 500 along line 503 and bump along line
128. Until an updated input is applied along line 58, the adder 55 will
accumulate escapement counts as each character is applied along line 20.
The code output from current data register 51 is also applied along line 67
to AND gate 68. The other input to gate 68 is along line 32 from AND gate
33. The inputs to AND gate 33 are NOT backspace along line 69, NOT tab
along line 125, and NOT end of line along line 126. When an up signal is
applied along line 32, the code appearing on line 67 is gated along line
127 to output data store register 70. From output data store 70, the code
is applied along line 29 and written into intermediate buffer 24. This
writing into buffer 24 occurs upon the application of both a NOT
back-space signal along line 69 and a write data signal along line 72 to
AND gate 73. The output of AND gate 73 is along line 74 to output data
store 70 for causing the gating of the code stored in store 70 along line
29.
The location of the cursor is stored in cursor register 37 (FIG. 3). The
location count is output along line 61 to compare unit 62. In compare unit
62 a comparison is made with the current code position being addressed in
buffer 2. The current code position count is stored in counter 50 which is
incremented by a bump signal applied along line 80 as each code is
addressed along line 19. The count stored in counter 50 is applied along
line 63 to compare 62. When a compare occurs indicating that the counts
applied along lines 61 and 63 are equal, there will be an output signal
applied along line 64. This signal is then applied along the load line 65
to effect the loading of the cursor escapement register 66 with the
escapement count stored in register 57. This count will include the count
for the cursor character. Register 57 is connected to register 66 by line
60. The count in register 66 is then applied along line 91 to segmentation
logic block 90. Logic 90 is used for determining the segment, including
the cursor, which is to be displayed. This will be described in greater
detal when reference is made to FIG. 6.
The output of compare 62 is also applied along line 81 to AND gate 82. The
other input to AND gate 82 is along line 83 from intermediate buffer
pointer counter 78. Counter 78 is a resettable up/down counter. Counter 78
is set along line 79 to the beginning location of intermediate buffer 24
when the beginning of the line is read out of buffer 2. Counter 78 is
incremented for each character code upon a signal being applied along
either the write tab data line 109 or text line 75. Thus, the count stored
in counter 78 at any one time is the address count of the character being
written into buffer 24. Lines 75 and 109 are connected to OR gate 76 which
is in turn connected to counter 78 along the up line 77. A signal
appearing on the up line 77 for a character code appearing on line 20 will
result in counter 78 being incremented by one. A backspace code appearing
on line 20 will result in counter 78 being decremented by one due to a up
signal being applied along backspace line 113.
Upon a compare signal appearing on line 81, the count in counter 78 will be
gated through AND gate 82 and applied along line 84 to cursor logic block
85. The function and structure of block 85 will be more fully appreciated
when reference is made to FIG. 5. For now, the other inputs to block 85
are applied along lines 89 and 93. An up signal appears on line 89 when
there is both an indication along line 87 that the end of the current line
has been stored in buffer 24, and along line 86 that operation involves
the cursor line. These signals are applied to AND gate 88. The input along
line 93 to block 85 is from the output of block 90 along line 92. The
output from block 85 is along line 38.
When a tab code appears on line 20, it is stored in current data register
51. Thereafter, it is applied along line 52 to decode 53 for decoding. The
tab code is also applied along line 22 to escapement ROS 21. There is no
escapement for a tab stored in escapement ROS 21. Therefore, a zero output
is applied along line 23 to character escapement register 54. A zero is in
turn applied along line 56 to adder 55. The count remains the same in
adder 55 and is applied along line 58 to current total escapement 57 as
described above. The output of current total escapement 57 is applied
along line 112 to AND gate 506. The other input to AND gate 506 is tab
along line 504 from decode 53. The output of AND gate 506 is along line
507 to tab logic block 110. Tab logic 110 will be described in greater
detail when reference is made to FIG. 9. For now, tab logic 110 addresses
the tab stop array shown in FIG. 3 along line 18 and receives data back
along line 17. This is to determine the count of units of escapement to
the next set tab. When this count of units has been determined, an output
from tab logic 110 is applied along line 111 to adder 55. It is again to
be noted that tabs are not stored in buffer 24. The escapement unit count
is applied along line 111 to adder 55. Adder 55 is incremented for the
number of one escapement unit spaces to be input into buffer 24 for the
tab code read. The contents of adder 55 are then applied along line 58 to
current total escapement register 57. At this time, tab logic 110 causes
signals to be applied along the write tab data line 109 to OR gate 76, and
then along line 77 for incrementing intermediate buffer pointer 78 the
desired number of characters. Each time intermediate buffer pointer 78 is
incremented, the logic 110 outputs a space code along line 124 to output
data store 70. The intermediate buffer pointer 78 along line 25 is
repositioned to a point corresponding to the next set tab for the write in
of additional characters making up the line.
The output of segmentation logic block 90 along line 92 is applied along
line 94 to scale logic block 95. Other inputs to scale logic block 95 are
the locations of the left and right margins along lines 96 and 97,
respectively. These are derived from line 11 in FIG. 3. Another input to
scale logic block 95 is from output data store 70 along line 98. Further,
scale logic block 95 is in two-way communication along lines 17 and 18
with the tab stop array 16 shown in FIG. 3. One output from scale logic 95
is along line 99 to intermediate buffer pointer 78. The remaining outputs
of scale logic 95 are along lines 100, 101, and 102 to the stop, write,
and read registers 103, 104 and 105, respectively. The outputs of the
stop, write, and read registers 103-105 are along lines 106, 107, and 108,
respectively, to DMA 26. Block 95 will be discussed in greater detail when
reference is made to FIG. 7.
The occurrence of a backspace code results in an up signal being applied
along line 113 to intermediate buffer pointer counter 78. This is for
decrementing the pointer 25. The next incoming character code along line
29 to buffer 24 will then be written over the character code before the
backspace code. Also, the current total escapement count in register 57 is
adjusted dependent upon the read out of the escapement ROS 21 for the
backspace code.
The output of segmentation logic block 90 along line 92 is also applied
along line 114 to line move logic block 115. Another input to line
movement logic 115 is along line 116 from output data store 70. One output
of line move logic 115 is along line 117 to intermediate buffer pointer
counter 78. Line move logic 115 is also in communication with escapement
ROS 21 along lines 22 and 23. Another input to line move logic 115 is the
current line number along line 118. Other outputs from line move logic are
along address line 119 and data line 123 to refresh buffer 34, and along
lines 120, 121, 122, to stop, write and read registers 103, 104 and 105,
respectively. One point to note here is that the DMA 26 is not used in the
transfer of data along line 123 to refresh buffer 34. Block 115 will be
described in greater detail when reference is made to FIG. 8.
Cursor Logic
Reference is next made to FIG. 5 wherein there is shown the structure
included in the cursor logic block 85 of FIG. 4. The inputs to the cursor
logic are cursor line complete along line 89, the cursor address in
intermediate buffer along line 84, and current segment begin point from
the left margin along line 94. The current address of the cursor in the
intermediate buffer along line 84 is input to the cursor pointer register
60. The current segment begin point from the left margin along line 94 is
input to an adder 131. Referring back to FIG. 4, this is obtained from
segmentation logic block 90. The count stored in intermediate buffer start
address register 130 is a constant corresponding to the count for the
first character storage location in buffer 24. This count can be
representative of the location of the left margin setting. This count is
applied to adder 131 along line 132 for summing with the current segment
begin count from the left margin applied along line 94. The sum of the
counts applied along lines 94 and 132 is subtracted by subtractor 133 from
the count stored in the cursor pointer register 60. The count thus
obtained is applied along line 134 to cursor displacement register 135.
The count contained in cursor displacement register 135 is the count from
the beginning of the segment being worked on. This count is then applied
along line 136 to AND gate 137. The other input to AND gate 137 is along
line 89 indicating that the cursor line has been completed. The count in
register 135 is then applied along line 38 and stored in the cursor
register 37 (FIG. 3).
Segmentation Logic
Reference is next made to FIG. 6 wherein there is shown the structure
included in the segmentation logic block 90 of FIG. 4. It is noted that
segmentation logic 90 has one input along line 91. This input is a count
of the number of escapement units from the left margin to the cursor
position. The count is input to divider 140, and divided by a constant
stored and contained in constant register 141. The constant is applied to
divider 140 along line 142. Referring to the constant table in the upper
right hand corner, the value of the constant C1 is 5 escapement units.
This constant is the escapement count for spaces, symbols, and all
numerals. In addition, it is the count for scale symbols when operation is
in proportional spacing. Further, this count is the average number of
escapement units for each character in proportional spacing. Divider 140
is structured to output only whole numbers. Any remainder is in effect
discarded. The whole number output from divider 140 is applied along line
143 to cursor character count register 144. In terms of proportional
spacing, this whole number will be an equivalent number of 5 EU characters
from the left margin. For standard spacing this whole number will be the
exact number of characters from the left margin. The output of the cursor
character count register 144 is applied along line 145 to compare units
146, 147, 148 and 149. Other inputs to compare units 146-149 are from
constant registers C2-C9 designated by reference numerals 150-157 when
gated by constant select gates 159-162. Registers 150-157 contain the
escapement unit count shown in the table in the upper right hand corner.
These counts are applied to constant select gates 159-162. These gates are
structured to gate the count contained in constant registers 150, 152,
154, and 156 to compare units 146-149 when operation is in standard
spacing. When operation is in proportional spacing (PSM), a signal will be
applied along line 158 to these gates for causing the gating of the count
contained in registers 151, 153, 155, and 157 to compare units 146-149.
Considering constant select gate 159, for example, this can be made up of
AND gates for each register bit having one input from each bit of register
150 and an inverted input from line 158. The outputs of these register AND
gates are to additional OR gates and then to compare unit 146. Other
inputs to these additional OR gates would be from other AND gates having
inputs from line 158 and register 151.
The comparison in compare units 146-149 is with the cursor character count
from register 144 along line 145, and the selected set of registers
150-157. Referring again to compare unit 146, if the character count
applied along line 145 is less than, or equal to, the constant count from
the selected one of registers 150 and 151, then an output is applied along
the S1 line 163. If the character count along line 145 is greater than the
input constant count, then the output from compare 146 is applied along
line 164 to AND gate 165.
If an output is applied from compare 146 along the S1 line 163, this is
applied to OR gate 177. The output of OR gate 177 is a new first segment
(NS1) signal along line 178 to OR gate 179. It is to be noted here that
upon power "on", operation begins in the first segment. If a signal is
applied along line 178, operation remains in segment 1. The output of OR
gate 179 is along the bit zero (B0) line 180 to new segment number
register 190. Register 190 is a two bit register for storing the segment
number in binary form.
Referring back to AND gate 165, an output will be applied along the S12
line 167 when the cursor character count along line 145 is less than, or
equal to, the input constant from the selected one of constant registers
C3 and C7. An output along the S12 line 167 is applied to AND gates 199
and 201. Whether an output appears on either of lines 200 or 202 depends
upon the up or down inputs to AND gates 199 and 201 along the LS1 line 196
and the LS2 line 197. The derivation of the LS1 and LS2 inputs is from
decode 195. Assuming operation were initially in the first segment, the
first segment number would be stored in register 193 and an output would
appear along the LS1 line 196. The gating of the last segment number from
register 193 to decode 195 is along line 194. With the LS1 signal "up"
along line 196, and the S12 signal "up" along line 167, an "up" signal is
gated through AND gate 199, along line 200, through OR gate 177, and along
the NS1 line 178. This would result in a one being applied along the B0
line 180 to new segment number register 190. In this case, operation
remains in the first segment. Since the previously selected segment was
the first, the output from register 190 is along line 191 to register 193,
and the output of decode 195 is along the LS1 line 196. The output of
register 193 is along line 194 to decode 195 each time a new frame is to
be generated for display. When a new frame is to be generated, a new frame
signal is applied along line 192. The above discussion has been directed
toward outputs along either the S1 or S12 lines, and operation remaining
in the first segment.
Considering standard spacing, if the cursor is located between the left
margin which has a constant value of zero and C2 which has a constant
value of 62, the cursor will be located solely in the first segment. If
the cursor is located between C2 and C3, then it can be in either the
first or second segment. As pointed out above though, segmentation will
not occur unless the cursor is moved and caused to overrun one of the
segments. Therefore, for a cursor location between 0 and 83 escapement
units from the left margin, the operating segment will be the first
segment. If the cursor is moved to 84, then it will be located exclusively
in the second segment. If the cursor is moved to 87, then it can be
located in either the second or third segments. In this case, operation
will be in the lowest order segment which is the second segment. Although
not specifically pointed out, it was assumed in the above that forward
escapement was taking place. The rules are the same for reverse escapement
when the cursor is backspaced.
The output of segment begin constants ROS 211 is along line 212 to current
segment begin count register 213. For the first segment it will be zero,
for the second segment it will be 62, and for the third segment it will be
86. This is assuming operation in standard spacing. Corresponding values
are shown in the constant table for proportional spacing. The contents of
the current segment begin count register 213 are applied along line 92 to
the cursor logic block 85, scale logic block 95, and line move logic block
115 shown in FIG. 4.
Refer again to the constant select gates, and particularly the constant
select gate 160. If the cursor character count along line 145 is greater
than the constant selected by constant select gate 160 from constant
registers C3 and C7, an output is applied along line 168 to AND gate 170.
An "up" output along the S2 line 171 will not occur until there is an
output along line 169 from compare 148. The output along line 169 from
compare 148 denotes that the cursor character count from register 144 is
less than, or equal to, the selected constant stored or contained in
registers 154 and 155. When an output appears on the S2 line 171, it is
applied to OR gate 182. This denotes that operation is to be solely in the
second segment. The output of OR gate 182 is a new second segment (NS2)
signal applied along line 183 to OR gate 184. The output of OR gate 184 is
along the bit one (B1) line 185 to new segment number register 190. If the
previous operation were in the first segment, the output of decoder 195
would be along the LS1 line 196. This is due to the up output along the B0
line 180 as will be described later herein.
When operation begins in the second segment, the output of new segment
number register 190 is along line 191 to last segment number save register
193. This occurs when a new frame signal is applied along line 192. The
new frame signal along line 192 appears due to the fact that a new frame
must be generated for the second segment. The second segment number from
register 193 is applied along line 194 to decode 195. For the second
segment, the output of decode 195 is along the LS2 line 197 to AND gates
201 and 203. There are no outputs from AND gates 201 and 203 since the
inputs S12 and S23 are down.
If the output of compare 148 indicates that the cursor character count 144
along line 145 is greater than one of constants C4 and C8 selected by
constant select gate 161, an output is applied along line 172 to AND gate
174. For an "up" S23 output from AND gate 174 along line 175, there must
be an "up" output along line 173 from compare 149. This will occur when
the cursor character count along line 145 is less than, or equal to, the
selected constant from registers 156 and 157. The outputs of registers 156
and 157 are applied to constant select gate 162. When an output appears
along the S23 line 175, it is applied to both AND gates 203 and 205. Since
the last segment was the second segment, and an output appeared from
decode 195 along the LS2 line 197, AND gate 203 is the pertinent gate. The
output of AND gate 203 is along line 204 to OR gate 182. The output of OR
gate 182 is along the NS2 or new second segment line 183 to OR gate 184.
The output from OR gate 184 is along the bit one (B1) line 185 for
operation to continue in the second segment.
As the cursor is moved further to the right, there will ultimately be an
output along the S3 line 176. This is applied to OR gate 186. The output
of OR gate 186 is along the new third segment (NS3) lines 187 and 188 to
OR gates 184 and 179. The outputs of OR gates 184 and 179 are along lines
185 and 180 to register 190. Again, register 190 is a two bit register,
and it has 4 states (00, 01, 10, and 11). The 00 state is invalid (or not
used). The up outputs along lines 180 and 185 cause the storing of a state
in register 190 which is representative of the third segment. When
operation begins in the third segment, there is an output long the LS3
line 198 from decode 195, and this is applied to AND gate 205.
If the cursor is backspaced to a point where it can exist in either the
second or third segments, a signal is applied along the S23 line 175 to
AND gates 203 and 205. The other input to AND gate 203 is down. The output
of AND gate 205 is "up" and is along line 206 to OR gate 186. The output
of OR gate 186 is along the NS3 lines 187 and 188 to OR gates 184 and 179.
The one outputs from OR gates 179 and 184 are applied along lines 180 and
185 to in essence load a three into register 190. That is, register 190 is
set to one of the states described above. Operation remains in the third
segment. From the above, it is to be appreciated that upon either forward
or reverse escapement of the cursor, segmentation will not occur until the
cursor overruns a segment in either direction.
Scale Logic
Reference is next made to FIG. 7 wherein there is shown the structure
included in the scale logic block 95 of FIG. 4. This structure is used
first for reading the scale image, beginning with the left margin, out of
the scale image ROS 31 in FIG. 3 and writing it into the intermediate
buffer 24. Thereafter, this structure causes the appropriate segment of
the scale image to be read out of the intermediate buffer and written into
the refresh buffer 34.
To begin with, the left margin location, in terms of character count, is
read in along line 96 and applied to adder 232. To this count is added a
count stored in scale image pointer register 230. The count stored in
register 230 is the location being addressed in the scale image ROS 31.
This location count can be assumed to be a zero. The output of the scale
image pointer register 230 is applied along line 231 to adder 232. The sum
output from adder 232 is applied along line 233 to AND gate 236. This
determines the point in the scale image ROS 31 where reading by DMA 26 is
to begin. The other input to AND gate 236 is along the move select line
249. When the input along line 249 is up, the sum from adder 232 is
applied along line 102 to DMA 26. Before a signal is applied along line
249, the stop point in the ROS 31 and the write point in intermediate
buffer 24 must be determined. After all points are determined, the reading
of the scale image will begin at a point corresponding to the left margin
and the remainder of the scale image will be written in the intermediate
buffer 24.
Next, it must be determined where in the intermediate buffer 24 the
beginning of the scale line is to be written. Block 270 is a register
containing a constant which is the begin address in the intermediate
buffer. This can be assumed to be zero. This address is applied along line
275 to AND gate 239. When a move select signal is applied along line 249,
the begin address in the intermediate buffer 24 will be output along line
101 to DMA 26. This will control the writing of the appropriate beginning
of the scale image into the intermediate buffer.
The point at which the reading of ROS 31 is to stop is determined by the
count stored in constant register 247. This count is input to AND gate 244
along line 263. There are now inputs to AND gate 236, 239, and 244. An
input is now applied along the move select line 249, and outputs are
applied along lines 102, 101, and 100 to DMA 26. The scale image is now
read out of ROS 31 and written into buffer 24.
The scale logic is controlled by a four state sequence state counter 616
having an input applied along line 615 from OR gate 614. This input
controls the counter by causing it to be bumped to the next state. DMA
complete line 600 is applied to OR gate 614 and controls bumping between
states 0,0 and 0,1 and states 1,1 and 0,0. Refer to the sequence states
table in the upper right hand corner. DMA complete line 600 is generated
by the DMA 26 to signal that it has completed a read and write operation.
The outputs of the sequence state counter 616 along the CLK1 line 605 and
CLK2 line 606 are applied to exclusive OR gate 607. The output of
exclusive OR gate 607 is along line 608 to inverter 609. The output of
inverter 609 is along the move select line 249. CLK2 line 606 is also
applied to inverter 610. The output | | |
